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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l1-20020a170907914100b0087777d66a7fsi6390026ejs.61.2023.01.25.10.08.58; Wed, 25 Jan 2023 10:09:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=I1szdJ9l; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235819AbjAYR2P (ORCPT + 99 others); Wed, 25 Jan 2023 12:28:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235717AbjAYR2L (ORCPT ); Wed, 25 Jan 2023 12:28:11 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 275B339297; Wed, 25 Jan 2023 09:28:05 -0800 (PST) Received: from benjamin-XPS-13-9310.. (unknown [IPv6:2a01:e0a:120:3210:ad6f:c6af:709d:745c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7FF766602E6B; Wed, 25 Jan 2023 17:28:03 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674667683; bh=UHN+nMs+n4jX7nk2ZzasYi5PAlhbZHRCrcYcr8lRebA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I1szdJ9lC4AAKuPFpGQI7T1K3ti7RHHil3Bu5WfSZomIMrn2o8GPyb/QHSEd1TdZA iDjE9JcVNOvcByd57GM3DwsCqIRZL4c4Z5ZgpIZ2yVj4xQFZ7zAusng1C31iCdQvWb 7ROxHwQemOXEP1XxoN79/QA9r5NUj2bhjrsnf6n1BVisMfLMd5DPX0NhTOrXN5M6QA 59PIRKO2Jnpy71cquvWqvV/1cAgoh2Sya/R+tU1aghGKytd9lQnTLRLxVn+DDgHmNe 6WWRHohD08Q7QEWiPGndXseBX9TaY+6D2CVmAWO7jC0bA7R/2OMNz7BMTyRHyihRxZ 6/myLYfkOd6uA== From: Benjamin Gaignard To: ezequiel@vanguardiasur.com.ar, p.zabel@pengutronix.de, mchehab@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, hverkuil-cisco@xs4all.nl, nicolas.dufresne@collabora.co.uk Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v4 2/2] media: verisilicon: HEVC: Only propose 10 bits compatible pixels formats Date: Wed, 25 Jan 2023 18:27:55 +0100 Message-Id: <20230125172755.1498973-3-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230125172755.1498973-1-benjamin.gaignard@collabora.com> References: <20230125172755.1498973-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756018939869187302?= X-GMAIL-MSGID: =?utf-8?q?1756018939869187302?= When decoding a 10bits bitstreams HEVC driver should only expose 10bits pixel formats. To fulfill this requirement it is needed to call hantro_reset_raw_fmt() when bit depth change and to correctly set match_depth in pixel formats enumeration. Signed-off-by: Benjamin Gaignard Reviewed-by: Nicolas Dufresne --- version 4: - Only set ctx->bit_depth when hantro_reset_raw_fmt() returns is ok. .../media/platform/verisilicon/hantro_drv.c | 46 +++++++++++++++---- .../media/platform/verisilicon/imx8m_vpu_hw.c | 2 + 2 files changed, 40 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 8cb4a68c9119..30abab7ac9bf 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -251,11 +251,6 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) { - struct hantro_ctx *ctx; - - ctx = container_of(ctrl->handler, - struct hantro_ctx, ctrl_handler); - if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; @@ -274,8 +269,6 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) /* Only 8-bit and 10-bit are supported */ return -EINVAL; - - ctx->bit_depth = sps->bit_depth_luma_minus8 + 8; } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; @@ -286,6 +279,38 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) return 0; } +static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct hantro_ctx *ctx; + + ctx = container_of(ctrl->handler, + struct hantro_ctx, ctrl_handler); + + vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); + + switch (ctrl->id) { + case V4L2_CID_STATELESS_HEVC_SPS: + { + const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; + int bit_depth = sps->bit_depth_luma_minus8 + 8; + int ret; + + if (ctx->bit_depth == bit_depth) + return 0; + + ret = hantro_reset_raw_fmt(ctx, bit_depth); + if (!ret) + ctx->bit_depth = bit_depth; + + return ret; + } + default: + return -EINVAL; + } + + return 0; +} + static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) { struct hantro_ctx *ctx; @@ -328,6 +353,11 @@ static const struct v4l2_ctrl_ops hantro_ctrl_ops = { .try_ctrl = hantro_try_ctrl, }; +static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { + .s_ctrl = hantro_hevc_s_ctrl, + .try_ctrl = hantro_try_ctrl, +}; + static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = { .s_ctrl = hantro_jpeg_s_ctrl, }; @@ -470,7 +500,7 @@ static const struct hantro_ctrl controls[] = { .codec = HANTRO_HEVC_DECODER, .cfg = { .id = V4L2_CID_STATELESS_HEVC_SPS, - .ops = &hantro_ctrl_ops, + .ops = &hantro_hevc_ctrl_ops, }, }, { .codec = HANTRO_HEVC_DECODER, diff --git a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c index b390228fd3b4..f850d8bddef6 100644 --- a/drivers/media/platform/verisilicon/imx8m_vpu_hw.c +++ b/drivers/media/platform/verisilicon/imx8m_vpu_hw.c @@ -152,6 +152,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_NV12, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH, @@ -165,6 +166,7 @@ static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { { .fourcc = V4L2_PIX_FMT_P010, .codec_mode = HANTRO_MODE_NONE, + .match_depth = true, .postprocessed = true, .frmsize = { .min_width = FMT_MIN_WIDTH,