[v2] cxl: fix spelling mistakes

  Correct spelling mistakes (reported by codespell).

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Alison Schofield <alison.schofield@intel.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>
Cc: Ben Widawsky <bwidawsk@kernel.org>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: linux-cxl@vger.kernel.org
---
v2: add corrections for other source-code spelling errors (Alison)

 drivers/cxl/Kconfig       |    2 +-
 drivers/cxl/acpi.c        |    2 +-
 drivers/cxl/core/port.c   |    2 +-
 drivers/cxl/core/region.c |    2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)
  

On Tue, Jan 24, 2023 at 07:22:21PM -0800, Randy Dunlap wrote:
> Correct spelling mistakes (reported by codespell).
> 
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Alison Schofield <alison.schofield@intel.com>
> Cc: Vishal Verma <vishal.l.verma@intel.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Cc: Ben Widawsky <bwidawsk@kernel.org>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Cc: linux-cxl@vger.kernel.org
> ---
> v2: add corrections for other source-code spelling errors (Alison)

Thanks Randy,
Reviewed-by: Alison Schofield <alison.schofield@intel.com>

> 
>  drivers/cxl/Kconfig       |    2 +-
>  drivers/cxl/acpi.c        |    2 +-
>  drivers/cxl/core/port.c   |    2 +-
>  drivers/cxl/core/region.c |    2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff -- a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> --- a/drivers/cxl/Kconfig
> +++ b/drivers/cxl/Kconfig
> @@ -116,7 +116,7 @@ config CXL_REGION_INVALIDATION_TEST
>  	depends on CXL_REGION
>  	help
>  	  CXL Region management and security operations potentially invalidate
> -	  the content of CPU caches without notifiying those caches to
> +	  the content of CPU caches without notifying those caches to
>  	  invalidate the affected cachelines. The CXL Region driver attempts
>  	  to invalidate caches when those events occur.  If that invalidation
>  	  fails the region will fail to enable.  Reasons for cache
> diff -- a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -19,7 +19,7 @@ struct cxl_cxims_data {
>  
>  /*
>   * Find a targets entry (n) in the host bridge interleave list.
> - * CXL Specfication 3.0 Table 9-22
> + * CXL Specification 3.0 Table 9-22
>   */
>  static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
>  			  int ig)
> diff -- a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1137,7 +1137,7 @@ static struct cxl_port *find_cxl_port_at
>  }
>  
>  /*
> - * All users of grandparent() are using it to walk PCIe-like swich port
> + * All users of grandparent() are using it to walk PCIe-like switch port
>   * hierarchy. A PCIe switch is comprised of a bridge device representing the
>   * upstream switch port and N bridges representing downstream switch ports. When
>   * bridges stack the grand-parent of a downstream switch port is another
> diff -- a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -399,7 +399,7 @@ static ssize_t interleave_granularity_st
>  	 * When the host-bridge is interleaved, disallow region granularity !=
>  	 * root granularity. Regions with a granularity less than the root
>  	 * interleave result in needing multiple endpoints to support a single
> -	 * slot in the interleave (possible to suport in the future). Regions
> +	 * slot in the interleave (possible to support in the future). Regions
>  	 * with a granularity greater than the root interleave result in invalid
>  	 * DPA translations (invalid to support).
>  	 */
  

On Tue, 2023-01-24 at 19:22 -0800, Randy Dunlap wrote:
> Correct spelling mistakes (reported by codespell).
> 
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Alison Schofield <alison.schofield@intel.com>
> Cc: Vishal Verma <vishal.l.verma@intel.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Cc: Ben Widawsky <bwidawsk@kernel.org>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Cc: linux-cxl@vger.kernel.org
> ---
> v2: add corrections for other source-code spelling errors (Alison)
> 
>  drivers/cxl/Kconfig       |    2 +-
>  drivers/cxl/acpi.c        |    2 +-
>  drivers/cxl/core/port.c   |    2 +-
>  drivers/cxl/core/region.c |    2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)

Looks good,
Reviewed-by: Vishal Verma <vishal.l.verma@intel.com>

> 
> diff -- a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> --- a/drivers/cxl/Kconfig
> +++ b/drivers/cxl/Kconfig
> @@ -116,7 +116,7 @@ config CXL_REGION_INVALIDATION_TEST
>         depends on CXL_REGION
>         help
>           CXL Region management and security operations potentially invalidate
> -         the content of CPU caches without notifiying those caches to
> +         the content of CPU caches without notifying those caches to
>           invalidate the affected cachelines. The CXL Region driver attempts
>           to invalidate caches when those events occur.  If that invalidation
>           fails the region will fail to enable.  Reasons for cache
> diff -- a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -19,7 +19,7 @@ struct cxl_cxims_data {
>  
>  /*
>   * Find a targets entry (n) in the host bridge interleave list.
> - * CXL Specfication 3.0 Table 9-22
> + * CXL Specification 3.0 Table 9-22
>   */
>  static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
>                           int ig)
> diff -- a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1137,7 +1137,7 @@ static struct cxl_port *find_cxl_port_at
>  }
>  
>  /*
> - * All users of grandparent() are using it to walk PCIe-like swich port
> + * All users of grandparent() are using it to walk PCIe-like switch port
>   * hierarchy. A PCIe switch is comprised of a bridge device representing the
>   * upstream switch port and N bridges representing downstream switch ports. When
>   * bridges stack the grand-parent of a downstream switch port is another
> diff -- a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -399,7 +399,7 @@ static ssize_t interleave_granularity_st
>          * When the host-bridge is interleaved, disallow region granularity !=
>          * root granularity. Regions with a granularity less than the root
>          * interleave result in needing multiple endpoints to support a single
> -        * slot in the interleave (possible to suport in the future). Regions
> +        * slot in the interleave (possible to support in the future). Regions
>          * with a granularity greater than the root interleave result in invalid
>          * DPA translations (invalid to support).
>          */
  

Randy Dunlap wrote:
> Correct spelling mistakes (reported by codespell).
> 
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Alison Schofield <alison.schofield@intel.com>
> Cc: Vishal Verma <vishal.l.verma@intel.com>
> Cc: Ira Weiny <ira.weiny@intel.com>
> Cc: Ben Widawsky <bwidawsk@kernel.org>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Cc: linux-cxl@vger.kernel.org
> ---
> v2: add corrections for other source-code spelling errors (Alison)

Applied for 6.3, thanks Randy!