[V2,1/2] arm64: dts: ti: k3-j721s2-mcu-wakeup: Fix IO PADCONFIG size for wakeup domain
| Message ID | 20230124120311.7323-2-sinthu.raja@ti.com |
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From: Sinthu Raja <sinthu.raja@mistralsolutions.com>
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Subject: [PATCH V2 1/2] arm64: dts: ti: k3-j721s2-mcu-wakeup: Fix IO PADCONFIG
size for wakeup domain
Date: Tue, 24 Jan 2023 17:33:10 +0530
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| Series |
Fix WKUP domain IO PADCONFIG size issue and RPi header support
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Commit Message
Sinthu Raja
Jan. 24, 2023, 12:03 p.m. UTC
From: Sinthu Raja <sinthu.raja@ti.com> The size of wkup domain I/O PADCONFIG register set is incorrect for J721S2. Therefore, update the PADCONFIG total offset size to the correct value for J721S2 SoC. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> --- Changes in V2: - Update commit description. - Update the offset value to 0x194 as 0x190 is the last register of the IO PADCONFIG register set. arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 0af242aa9816..b10f1e8b98e6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -50,7 +50,7 @@ mcu_ram: sram@41c00000 { wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x194>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>;