From patchwork Fri Jan 20 09:20:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 46250 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp98275wrn; Fri, 20 Jan 2023 01:24:17 -0800 (PST) X-Google-Smtp-Source: AMrXdXvKtcxTnXEd0lYSbOvzBWA4xOwP3YIhk0w40Ed9M6D9WS1pFf5ZxaG99qMV/5HhjJfFsyzO X-Received: by 2002:a17:906:f6ce:b0:877:9b5a:bd51 with SMTP id jo14-20020a170906f6ce00b008779b5abd51mr2064733ejb.72.1674206656990; Fri, 20 Jan 2023 01:24:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674206656; cv=none; d=google.com; s=arc-20160816; b=bCTVW3KpdlWAFV8stU0uywyw2NSOaRaQ5FYRP+L4tkq4eFnKmhQjiLMrfG3xfLbeDV WisO4O2Fq4PObv+tLKdVYm+cLtviEteylsTo2GUJdmaUmbUii9SOnfs58t4+vYRvsCQh 7e1t380dkMsABO6xOwRyWl/tEJ8Vg32ctnENCxvSv8Lql9hbaZ4/4t1k7YpIK0su/oDK fcH1tCvxkFmKvFIQ8lXIegh+uv6/mnUqNsRr/MUK3bT0IDg5/ABQDlVKsKFZcXlBDANp +ndJYABI+3mmJUTa2+cNyhm7DOJGtz2KoJPI/vQPIxDXWyU6wwMyWQkyOqvw/L285uUq JjMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LjxtQm9yGz6MJPuXyRMk0bzwYVSnoLlNx3J1i1Kq8ro=; b=xK8fxc6ikcbUBzLm3tvSAH1EUkamGKBQAWBcIgI8d8eb2UnhuM/+l/5UxeSZS98tAX bqT788J6FWuw9yDtfbPLQSfm3qjT1bVW1coHgw+QzQnb6J0eWNpohYTOMz/spJB725WH +/a9wAgHcnqrenLwKx4xbLYTQnmSyU0RiMD5719DYOuPz/PgkQx0u1Zzl9Y2vbnm14LG pxsbbFUbS9Nvn6F3rAn8ht5l9pRf+ksFJzGwOuQoadF5Hg173vVHhu9yCMwhEpOBMciY D/drRuqx0TYig8ioy6nSOsKk0QDrM3R4SEizJ75q3yuw3/TZ9nkqmKG2/TnQm35uhBG2 RfwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=KnpU2UKU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id nd23-20020a170907629700b007c08bfea555si44533195ejc.121.2023.01.20.01.23.53; Fri, 20 Jan 2023 01:24:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=KnpU2UKU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230323AbjATJXG (ORCPT + 99 others); Fri, 20 Jan 2023 04:23:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230408AbjATJWT (ORCPT ); Fri, 20 Jan 2023 04:22:19 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36D48966D3; Fri, 20 Jan 2023 01:21:39 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 997906602E8E; Fri, 20 Jan 2023 09:21:21 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674206483; bh=TXsvpuYEwVayUGP6yTdMIQtVttt74SBr+RVJGfEefQQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KnpU2UKUHHOdVtqDj350MN+FIuePsNaXgLcilcaOUEQsYyFgwXj076hIe2ck5QZDn F/wVTYuThbymeWjdhfV1eTD0OIw3gPkLCvkfeFdNTyah5Q+ESNA0Z7+homEytIGpNz UiPTgMK/Vq6yShR01/rG06xiU3GPpc6+rPWlDiJokY3iedxyU9gB33kGFo5JqfxznM QnOOxIiVHk6d2b5XGAyDRhW4p33pxN0NAhEfSVJyc8pQ+w8HZpwPM+EenqrchXMbI/ gnPq1cyIV0VhwWpj5Oemu9xoeluXsOv4u0gn8NszP6I5lGecOaiqZQ4gUkZ5S0vsKh cw43oMzeCUNKw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v4 14/23] clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs Date: Fri, 20 Jan 2023 10:20:44 +0100 Message-Id: <20230120092053.182923-15-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120092053.182923-1-angelogioacchino.delregno@collabora.com> References: <20230120092053.182923-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755532919118821501?= X-GMAIL-MSGID: =?utf-8?q?1755532919118821501?= This driver is registered early in clk_mt8192_top_init_early() and then again in clk_mt8192_top_probe(): the difference between the two is that the early one is probed with CLK_OF_DECLARE_DRIVER and the latter is regularly probed as a platform_driver. Knowing that it is not necessary for this platform to register the TOP_CSW_F26M_D2 clock that early, move it to top_divs and register it with the others during platform_driver probe for topckgen; While at it, since the only reason why the early probe existed was to register that clock, remove that entirely - leaving this driver to use only platform_driver. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen Reviewed-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8192.c | 39 ++++++------------------------- 1 file changed, 7 insertions(+), 32 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index ea4164c0995e..d012a229274e 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -26,10 +26,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000), }; -static const struct mtk_fixed_factor top_early_divs[] = { - FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2), -}; - static const struct mtk_fixed_factor top_divs[] = { FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0), FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0), @@ -95,6 +91,7 @@ static const struct mtk_fixed_factor top_divs[] = { FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10), FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16), FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20), + FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2), FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1), FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0), FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2, 0), @@ -1047,27 +1044,6 @@ static const struct mtk_pll_data plls[] = { 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), }; -static struct clk_hw_onecell_data *top_clk_data; - -static void clk_mt8192_top_init_early(struct device_node *node) -{ - int i; - - top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!top_clk_data) - return; - - for (i = 0; i < CLK_TOP_NR_CLK; i++) - top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data); - - of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); -} - -CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen", - clk_mt8192_top_init_early); - /* Register mux notifier for MFG mux */ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) { @@ -1093,6 +1069,7 @@ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) static int clk_mt8192_top_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *top_clk_data; int r; void __iomem *base; @@ -1100,17 +1077,17 @@ static int clk_mt8192_top_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); + top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); + if (!top_clk_data) + return; + r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data); if (r) return r; - r = mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data); - if (r) - goto unregister_fixed_clks; - r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); if (r) - goto unregister_early_factors; + goto unregister_fixed_clks; r = mtk_clk_register_muxes(&pdev->dev, top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, @@ -1156,8 +1133,6 @@ static int clk_mt8192_top_probe(struct platform_device *pdev) mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data); unregister_factors: mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); -unregister_early_factors: - mtk_clk_unregister_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data); unregister_fixed_clks: mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);