From patchwork Thu Jan 19 03:51:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 45583 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp136489wrn; Wed, 18 Jan 2023 20:29:14 -0800 (PST) X-Google-Smtp-Source: AMrXdXvsCm+owpMEjFV2/45n2puvGqCEo7oI2XuPBL2SYup9zAUNvmCNF+gunjXwONCIpXnBGqdP X-Received: by 2002:a17:907:8999:b0:7ad:b286:2184 with SMTP id rr25-20020a170907899900b007adb2862184mr9791575ejc.71.1674102554700; Wed, 18 Jan 2023 20:29:14 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1674102554; cv=pass; d=google.com; s=arc-20160816; b=mTlvSdw0COXJY51v3/x/FJb5D7nXbDzKWZxD5nQ65FR/L52IKIRWKJfxm3MKxO9OSC sulqd5ppuqI4f6s8YGwhqBS6+SAy00UGMJwgEqfZwLe61kQN7KWg/9Cu7wesub+tjeif M9k2Bg7nAoBgeB/IjDEdCgZiwzzdkd1Y2lmujk1ZqMqZTD3Yw3bUaFV+eLrAkIOf74rq nZ+AXhKSR5UsorKMa+IR4qBTo9zLNHv0XiqOnCogk570GHebRJmJNMIwEH011m3itFHp PRbskjhhknK1ktqpvr2PRChv6nGKSoYzrOBaaK7RPsXfGkALPHsXJ/zqxay4i8f/3c4U xQTQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=CbqxDJadqrHHWLEsqeIAFGgTZLiSV774ziT3BrEvhqw=; b=FgV4wb+OzOHBM2I7yM4viCoWXPGXTszziatiNa4Ll6mYjhEp9ZB8OyIiKa5xYWCxx9 nFPd4hMFME96NxyfCbFgp8b4k0AsqT6XYqPP051KAdSf48vCZ3QdobVAqrApzG4z7D3L AU7HMgQVVR0ZbBeafOxgy+XtLn9tPfE4K8YQFvPlp4tYCPiGB82bVWbbvDS1O4MA4lRW 5tplA97FhT6DU5m7BNUfQ0NBVm48vIwkrkR44lVjqG7p6r4GjpL9n+1la+vFwYXlGt9D j7NxVrSRh1WDmdzDhUC18/agooGBA6NZf9zW0JzksLThmhZkRcYV3VaGn6IyLD3dpoFK efaw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=hYh5QJqc; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hv13-20020a17090760cd00b0084c83d43fd6si42773448ejc.700.2023.01.18.20.28.50; Wed, 18 Jan 2023 20:29:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=hYh5QJqc; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229772AbjASE2J (ORCPT + 99 others); Wed, 18 Jan 2023 23:28:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230182AbjASEJA (ORCPT ); Wed, 18 Jan 2023 23:09:00 -0500 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on20629.outbound.protection.outlook.com [IPv6:2a01:111:f400:7e89::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EF7F4CE67; Wed, 18 Jan 2023 20:03:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jjKRn8sg94A59Jjx2A0wFQA49U9IA01ve9GUF9pdt5Jeu5ti98gMMfVvhOyM+NcaNZ9mu2HaRQGK+ng5yCSfetoG1d1BXFaudyo7ZnpgUng+QzIFIGQgrR/DDCmLiPtPwM1irZLr3TLOWKnUbCahm1zbrVnaDCgyE6+YhzZzsGu5YzCDDWhSiK+im41/P+NYF2uVSLOtWG+ZyT8VNWMmRHNhR68YuTF3IljGGVgB+7zwTRzJUvBZf+2Pp6qt2mdKJN+JjekVMbQRRWmJ4XQSEy0mZQts6ssGiM91cJnc3Vl0WFzwyY/30OAeK5Ioda3UMeb+F6HBhGIdXpfmQdHVwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CbqxDJadqrHHWLEsqeIAFGgTZLiSV774ziT3BrEvhqw=; b=YTtcwAbt37xFpVOkudryQiJk9+5y/jl3LGC7veaxgkhNYORxkpJ9dtSlCSOYTXhgiwWIcYGzYc9lCyaSX5WNltiJYR/QmryMoJw1kOaD/+Xu6DToY6aHzMWxEWwga7ZAnBK9VNpdESsYoDwSEG7XJSH8NlYADPE3VxhV91abxZbf61V/J73N++H1EQaEAfrTE8p9dAdL6SzCz7GnxGocB8DbkaSC9SGI0k7tN8aTCPm3nJnxRaRrItLZBxaDcpKuMhmS3nypE1WC/LhRXen2KENRMCAbmR2rKt/bWPEx3LSsZjaxRrCTIsu3kckEnPMG/HLkXbI6KVj7qHKJlgVfOQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.infradead.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CbqxDJadqrHHWLEsqeIAFGgTZLiSV774ziT3BrEvhqw=; b=hYh5QJqcUkfQj5A0ZkQIg1QXGGcaTshq9LZbUxyO58U8gIMUZB0YUTrQR9gurwRjfau28VIZzCfbZ6EqmOVN1KPCcNmdkdk5oPWBXlLq+FXe8K/N+ms8CIVjwZ7CHZ3ZEW9LJ3MRgzLSXCI4eDfCQtuOQ6jtx31bCubiu9gQPTc= Received: from MW4PR04CA0320.namprd04.prod.outlook.com (2603:10b6:303:82::25) by DS7PR12MB8249.namprd12.prod.outlook.com (2603:10b6:8:ea::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5986.23; Thu, 19 Jan 2023 03:53:00 +0000 Received: from CO1NAM11FT027.eop-nam11.prod.protection.outlook.com (2603:10b6:303:82:cafe::84) by MW4PR04CA0320.outlook.office365.com (2603:10b6:303:82::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.19 via Frontend Transport; Thu, 19 Jan 2023 03:53:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT027.mail.protection.outlook.com (10.13.174.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6002.13 via Frontend Transport; Thu, 19 Jan 2023 03:52:59 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 18 Jan 2023 21:52:56 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Date: Wed, 18 Jan 2023 19:51:34 -0800 Message-ID: <20230119035136.21603-14-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119035136.21603-1-blarson@amd.com> References: <20230119035136.21603-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT027:EE_|DS7PR12MB8249:EE_ X-MS-Office365-Filtering-Correlation-Id: 04ee84fc-d626-468e-b6bb-08daf9d0a858 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: B3R2yumuqZgFzcecbh2Mk0/O77KzzU40GVKbWHw3op1Bz7GEOlFXwS3IOuHfv7Z1+cuMgHPnAfqGdX5/iKH2DyxoJbGU6ZXG4ASPy3hHY31YW1t2FP+3DM0g92yS2o70GZ/5cJu1Yp3ZH9+MH+MP9xlC6DCBTGBpLToNzeBx0cOJymQdahAxKwx9YD5PLrPbSKaq1ITm50qkFUjEmvjtUR1rKHueERjCaDRkcvgUK9tEMm/V+4cHeAZfybWu4Pxt2W4UOmY8MEJu+TGpaL5zVfp0BOO6rmCiiniRmUOTHwtZ8nCftNRrZCNntlUiLCftHTQ9oxZn8K47Z0QMd7+OwVMx8/f+N6KsOhV9dT/1MRMm7TleNyHEGLKGvJ1aneN/OziMtEktJhsCGk7cWwq3nQN5u57f54lRLe8QI86vmu/n75YTIkviDjNZqZwNp83UrF+nAGcER4Y1M8+8WZVDzBuUJBj3L+PHX4wIMNR+Z35RoW82mF2qMzqWw/0XCp7iuO5Lpoul9HKBTmUPKS4VHFQ8eufidRl5CU31aza34soklEihVkQbd3NHsORAB1WUJydLjv8yhkIqV0e1wEiN0oh0DpcbyWBmicC7r37E9sA7s2orGOxJAwd/0Z5S8G0v2dxKT+IlfacdP3OX1/gRUrPMOOS5V6qI/rInINW5PvrfKvDPDPzpyzBa6YZZAnWtVB/sD/V25tpfKt5Ni7/TKg3wosSPJWntBmKwy50L8Z4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(346002)(396003)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(82310400005)(4326008)(2616005)(426003)(47076005)(6916009)(41300700001)(16526019)(70206006)(70586007)(26005)(8676002)(186003)(83380400001)(7416002)(316002)(2906002)(6666004)(478600001)(7406005)(356005)(40480700001)(54906003)(40460700003)(81166007)(36860700001)(336012)(8936002)(1076003)(82740400003)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:59.7840 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04ee84fc-d626-468e-b6bb-08daf9d0a858 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8249 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1755423760770936644?= X-GMAIL-MSGID: =?utf-8?q?1755423760770936644?= Add support for AMD Pensando Elba SoC which explicitly controls byte-lane enables on writes. Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which allows Elba SoC sdhci_elba_ops to overwrite the SDHCI IO memory accessors. Signed-off-by: Brad Larson --- Changes since v6: - Previously patch 16/17 --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 131 ++++++++++++++++++++++++++++--- 2 files changed, 123 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 5e19a961c34d..9e41115cc753 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Cadence SD/SDIO/eMMC driver. diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 708d4297f241..e92aa79a8be2 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; @@ -77,6 +79,11 @@ struct sdhci_cdns_phy_cfg { u8 addr; }; +struct sdhci_cdns_drv_data { + int (*init)(struct platform_device *pdev); + const struct sdhci_pltfm_data pltfm_data; +}; + static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, @@ -316,6 +323,92 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, sdhci_set_uhs_signaling(host, timing); } +/* Elba control register bits [6:3] are byte-lane enables */ +#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) + +/* + * The Pensando Elba SoC explicitly controls byte-lane enabling on writes + * which includes writes to the HRS registers. + */ +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables = GENMASK(1, 0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables = BIT(0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops = { + .write_l = elba_write_l, + .write_w = elba_write_w, + .write_b = elba_write_b, + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + struct resource *iomem; + void __iomem *ioaddr; + + host->mmc->caps |= (MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA); + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!iomem) + return -ENOMEM; + + /* Byte-lane control register */ + ioaddr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + + priv->ctl_addr = ioaddr; + priv->priv_writel = elba_priv_writel; + spin_lock_init(&priv->wrlock); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops = { .set_clock = sdhci_set_clock, .get_timeout_clock = sdhci_cdns_get_timeout_clock, @@ -325,13 +418,24 @@ static const struct sdhci_ops sdhci_cdns_ops = { .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, }; -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = { - .ops = &sdhci_cdns_ops, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, }; -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { - .ops = &sdhci_cdns_ops, +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = { + .init = elba_drv_init, + .pltfm_data = { + .ops = &sdhci_elba_ops, + }, +}; + +static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + }, }; static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, @@ -357,7 +461,7 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; - const struct sdhci_pltfm_data *data; + const struct sdhci_cdns_drv_data *data; struct sdhci_pltfm_host *pltfm_host; struct sdhci_cdns_priv *priv; struct clk *clk; @@ -376,10 +480,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev) data = of_device_get_match_data(dev); if (!data) - data = &sdhci_cdns_pltfm_data; + data = &sdhci_cdns_drv_data; nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node); - host = sdhci_pltfm_init(pdev, data, + host = sdhci_pltfm_init(pdev, &data->pltfm_data, struct_size(priv, phy_params, nr_phy_params)); if (IS_ERR(host)) { ret = PTR_ERR(host); @@ -397,6 +501,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev) host->ioaddr += SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; + if (data->init) { + ret = data->init(pdev); + if (ret) + goto free; + } sdhci_enable_v4_mode(host); __sdhci_read_caps(host, &version, NULL, NULL); @@ -461,7 +570,11 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops = { static const struct of_device_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc", - .data = &sdhci_cdns_uniphier_pltfm_data, + .data = &sdhci_cdns_uniphier_drv_data, + }, + { + .compatible = "amd,pensando-elba-sd4hc", + .data = &sdhci_elba_drv_data, }, { .compatible = "cdns,sd4hc" }, { /* sentinel */ }