[v3,4/8] phy: qcom-qmp: pcs-pcie: Add v6 register offsets
Commit Message
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated
header file.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 +++++++++++++++
2 files changed, 16 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
Comments
On 18/01/2023 02:53, Abel Vesa wrote:
> The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
> UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated
> header file.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 +
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 +++++++++++++++
> 2 files changed, 16 insertions(+)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
@@ -29,6 +29,7 @@
#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
#include "phy-qcom-qmp-pcs-pcie-v5.h"
#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
+#include "phy-qcom-qmp-pcs-pcie-v6.h"
#include "phy-qcom-qmp-pcie-qhp.h"
/* QPHY_SW_RESET bit */
new file mode 100644
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V6_H_
+
+/* Only for QMP V6 PHY - PCIE have different offsets than V5 */
+#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
+#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14
+#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
+#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
+
+#endif