diff mbox series

[v1,2/3] x86/MCE/AMD: Add HWID Fixup for PCS_XGMI SMCA

Message ID 20230116191102.4226-3-avadnaik@amd.com
State New
Headers
Series Update SMCA Error Decoding for AMD EPYC Processors |

Commit Message

Naik, Avadhut Jan. 16, 2023, 7:11 p.m. UTC 
  On AMD systems, during Scalable MCA (SMCA) initialization, the HWID and
McaType tuple, read from MCA_IPID register of a SMCA bank type, is used
by the kernel for populating the per-CPU smca_banks array. This very array
is, in turn being utilized by the edac_mce_amd module for determining the
SMCA bank type while decoding a machine check error.

However, on some AMD CPUs, the HWID read from the MCA_IPID register
for XGMI Controller SMCA bank type does not match the value expected by
the kernel. Consequently, the smca_banks array is not populated for the
bank type resulting in the machine check errors on the bank type not being
decoded.

As a solution, set the HWID, obtained from the MCA_IPID register, of the
XGMI Controller SMCA bank type on affected CPUs, to the value expected by
the kernel to ensure that the machine check errors on the bank type are
correctly decoded.

Signed-off-by: Avadhut Naik <avadnaik@amd.com>
---
 arch/x86/kernel/cpu/mce/amd.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
diff mbox series

Patch

diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 23c5072fbbb7..b0cce0ce056c 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -249,6 +249,30 @@  static void default_deferred_error_interrupt(void)
 }
 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
 
+/*
+ * Errata encountered on AMD CPUs for some SMCA bank types requires fixup
+ * of HWID, read from MCA_IPID register, for accurate SMCA error decoding.
+ */
+static inline void fixup_hwid(unsigned int *hwid_mcatype)
+{
+	struct cpuinfo_x86 *c = &boot_cpu_data;
+
+	if (c->x86 == 0x19) {
+		switch (c->x86_model) {
+		/*
+		 * Handle discrepancy in HWID of kernel and MCA_IPID register
+		 * for XGMI Controller SMCA bank type
+		 */
+		case 0x30 ... 0x3F:
+			if (*hwid_mcatype == HWID_MCATYPE(0x80, 0x0))
+				*hwid_mcatype = HWID_MCATYPE(0x50, 0x0);
+			break;
+		default:
+			break;
+		}
+	}
+}
+
 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu)
 {
 	u32 low, high;
@@ -321,6 +345,8 @@  static void smca_configure(unsigned int bank, unsigned int cpu)
 	hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
 				    (high & MCI_IPID_MCATYPE) >> 16);
 
+	fixup_hwid(&hwid_mcatype);
+
 	for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
 		s_hwid = &smca_hwid_mcatypes[i];