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Wysocki" , Peter Zilstra , Andy Lutomirski , Andrew Cooper Subject: [PATCH v1 Part2 5/5] x86/microcode: Provide an option to override minrev enforcement Date: Fri, 13 Jan 2023 09:29:20 -0800 Message-Id: <20230113172920.113612-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230113172920.113612-1-ashok.raj@intel.com> References: <20230113172920.113612-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754930350392078085?= X-GMAIL-MSGID: =?utf-8?q?1754930350392078085?= Minimum Required Revision (minrev) is enforced strictly. All new patches will have a minrev that is not zero. But there might be a transition time for some that need this enforcement to be relaxed. When the override is enabled, the kernel will be tainted. Provide a debugfs variable to override the minrev enforcement. Signed-off-by: Ashok Raj Cc: LKML Cc: x86 Cc: Ingo Molnar Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner (Intel) Cc: Tom Lendacky Cc: Stefan Talpalaru Cc: David Woodhouse Cc: Benjamin Herrenschmidt Cc: Jonathan Corbet Cc: Rafael J. Wysocki Cc: Peter Zilstra (Intel) Cc: Andy Lutomirski Cc: Andrew Cooper --- This patch is optional. --- arch/x86/include/asm/microcode.h | 2 ++ arch/x86/kernel/cpu/microcode/core.c | 13 ++++++++++++- arch/x86/kernel/cpu/microcode/intel.c | 8 ++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 3d48143e84a9..d82f22d50ebd 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -16,6 +16,8 @@ struct ucode_patch { extern struct list_head microcode_cache; +extern bool override_minrev; + struct cpu_signature { unsigned int sig; unsigned int pf; diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 446ddf3fcc29..5ed60c6c8e8d 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -44,7 +45,9 @@ #define DRIVER_VERSION "2.2" static struct microcode_ops *microcode_ops; +static struct dentry *dentry_ucode; static bool dis_ucode_ldr = true; +bool override_minrev; bool initrd_gone; @@ -497,7 +500,11 @@ static ssize_t reload_store(struct device *dev, pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); ret = -EINVAL; - goto put; + + if (!override_minrev) + goto put; + + pr_err("Overriding minrev\n"); } tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); @@ -688,7 +695,11 @@ static int __init microcode_init(void) cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", mc_cpu_online, mc_cpu_down_prep); + dentry_ucode = debugfs_create_dir("microcode", NULL); + debugfs_create_bool("override_minrev", 0644, dentry_ucode, &override_minrev); + pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); + pr_info("Override minrev %s\n", override_minrev ? "enabled" : "disabled"); return 0; diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 68a3c5569cd2..172e1f166844 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -141,6 +141,14 @@ static int is_lateload_safe(struct microcode_header_intel *mc_header) { struct ucode_cpu_info uci; + /* + * If minrev is bypassed via debugfs, then allow late-load. + */ + if (override_minrev) { + pr_info("Bypassing minrev enforcement via debugfs\n"); + return 0; + } + /* * When late-loading, ensure the header declares a minimum revision * required to perform a late-load.