Message ID | 20230111093245.318745-2-milkfafa@gmail.com |
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State | New |
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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id u6-20020a170902714600b001769e6d4fafsm2001341plm.57.2023.01.11.01.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 01:33:11 -0800 (PST) From: Marvin Lin <milkfafa@gmail.com> To: krzysztof.kozlowski@linaro.org, robh+dt@kernel.org, bp@alien8.de, tony.luck@intel.com, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, benjaminfair@google.com, yuenn@google.com, venture@google.com, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, KWLIU@nuvoton.com, YSCHU@nuvoton.com, ctcchien@nuvoton.com, kflin@nuvoton.com, Marvin Lin <milkfafa@gmail.com> Subject: [PATCH v18 1/3] ARM: dts: nuvoton: Add node for NPCM memory controller Date: Wed, 11 Jan 2023 17:32:43 +0800 Message-Id: <20230111093245.318745-2-milkfafa@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111093245.318745-1-milkfafa@gmail.com> References: <20230111093245.318745-1-milkfafa@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754718738970597776?= X-GMAIL-MSGID: =?utf-8?q?1754718738970597776?= |
Series |
EDAC/nuvoton: Add NPCM memory controller driver
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Commit Message
Marvin Lin
Jan. 11, 2023, 9:32 a.m. UTC
Add node for memory controller present on Nuvoton NPCM SoCs. The
memory controller supports single bit error correction and double bit
error detection.
Signed-off-by: Marvin Lin <milkfafa@gmail.com>
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
Comments
On Wed, Jan 11, 2023 at 05:32:43PM +0800, Marvin Lin wrote: > Add node for memory controller present on Nuvoton NPCM SoCs. The > memory controller supports single bit error correction and double bit > error detection. > > Signed-off-by: Marvin Lin <milkfafa@gmail.com> > --- > arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) I guess this needs an Ack from OF folks if it is going to go through the EDAC tree ...
On 12/06/2023 13:04, Borislav Petkov wrote: > On Wed, Jan 11, 2023 at 05:32:43PM +0800, Marvin Lin wrote: >> Add node for memory controller present on Nuvoton NPCM SoCs. The >> memory controller supports single bit error correction and double bit >> error detection. >> >> Signed-off-by: Marvin Lin <milkfafa@gmail.com> >> --- >> arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++ >> 1 file changed, 7 insertions(+) > > I guess this needs an Ack from OF folks if it is going to go through the > EDAC tree ... It is preferred this goes via Nuvoton ARM SoC tree. I don't understand why this is first in the series - it's clearly wrong. Best regards, Krzysztof
On Mon, Jun 12, 2023 at 01:22:09PM +0200, Krzysztof Kozlowski wrote: > It is preferred this goes via Nuvoton ARM SoC tree. I don't understand > why this is first in the series - it's clearly wrong. Don't ask me... So the EDAC driver itself is self-contained so I can review it and you can pick it up with the rest, if it looks ok. That ok?
On 12/06/2023 14:01, Borislav Petkov wrote: > On Mon, Jun 12, 2023 at 01:22:09PM +0200, Krzysztof Kozlowski wrote: >> It is preferred this goes via Nuvoton ARM SoC tree. I don't understand >> why this is first in the series - it's clearly wrong. > > Don't ask me... > > So the EDAC driver itself is self-contained so I can review it and you > can pick it up with the rest, if it looks ok. > > That ok? Yes. Please review and take the EDAC driver and the bindings (2/3, they already have my ack). Marvin, Please route the DTS (1/3) via Nuvoton SoC tree. Best regards, Krzysztof
On Mon, Jun 12, 2023 at 02:09:33PM +0200, Krzysztof Kozlowski wrote:
> Please route the DTS (1/3) via Nuvoton SoC tree.
Don't all three need to go together?
On 12/06/2023 14:39, Borislav Petkov wrote: > On Mon, Jun 12, 2023 at 02:09:33PM +0200, Krzysztof Kozlowski wrote: >> Please route the DTS (1/3) via Nuvoton SoC tree. > > Don't all three need to go together? No, the DTS is always independent because it describes the hardware. Linux should work fine regardless of hardware description. Tying Linux to specific DTS is usually sign of an ABI break. Best regards, Krzysztof
On Mon, Jun 12, 2023 at 03:00:19PM +0200, Krzysztof Kozlowski wrote: > No, the DTS is always independent because it describes the hardware. > Linux should work fine regardless of hardware description. Tying Linux > to specific DTS is usually sign of an ABI break. Ok, I see. Patches 2 and 3 queued for 6.5. Thx.
> Marvin, > Please route the DTS (1/3) via Nuvoton SoC tree. OK, will route the DTS via Nuvoton SoC tree. Thanks, Krzysztof! > Patches 2 and 3 queued for 6.5. Thanks, Boris!
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index c7b5ef15b716..d875e8ac1e09 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -179,6 +179,13 @@ fiux: spi@fb001000 { status = "disabled"; }; + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm750-memory-controller"; + reg = <0xf0824000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>;