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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ga10-20020a1709070c0a00b0084d7c9a5e5esi7072198ejc.101.2023.01.10.23.47.17; Tue, 10 Jan 2023 23:47:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=OiShJPUf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236599AbjAKHq5 (ORCPT + 99 others); Wed, 11 Jan 2023 02:46:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232030AbjAKHpr (ORCPT ); Wed, 11 Jan 2023 02:45:47 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA5BC11164; Tue, 10 Jan 2023 23:45:39 -0800 (PST) X-UUID: ecb00374918311ed945fc101203acc17-20230111 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=awJ9HuS9th8JLqrDSYQ68RRmYz+RJ4r58ZfeumDnQ00=; b=OiShJPUf9SXfnRxJ+iyLqHd5mfWw2tpYkhPUMZEj7Q2Z7pVn+gGVL3fDrpK+k/YmMapiDGTzext2bQBESNI+t1y1UnS0IGts9jE979t+ViEC+7C74fjLOfm42c97nU/v00ex66Ewst4o0KiWXjsUFQ3zTPSLI28rqbgyOWGBCYQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.17,REQID:3c223ad2-bb57-4c3c-bf68-3128c382348d,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:543e81c,CLOUDID:8199ee8b-8530-4eff-9f77-222cf6e2895b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: ecb00374918311ed945fc101203acc17-20230111 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1720019466; Wed, 11 Jan 2023 15:45:31 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 11 Jan 2023 15:45:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 11 Jan 2023 15:45:29 +0800 From: Roger Lu To: Matthias Brugger , Enric Balletbo Serra , Kevin Hilman , Nicolas Boichat CC: Fan Chen , Roger Lu , Jia-wei Chang , , , , , , Subject: [PATCH v4 01/14] soc: mediatek: mtk-svs: restore default voltages when svs_init02() fail Date: Wed, 11 Jan 2023 15:45:15 +0800 Message-ID: <20230111074528.29354-2-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230111074528.29354-1-roger.lu@mediatek.com> References: <20230111074528.29354-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754711470761825450?= X-GMAIL-MSGID: =?utf-8?q?1754711470761825450?= If svs init02 fail, it means we cannot rely on svs bank voltages anymore. We need to disable svs function and restore DVFS opp voltages back to the default voltages for making sure we have enough DVFS voltages. Fixes: 681a02e95000 ("soc: mediatek: SVS: introduce MTK SVS engine") Fixes: 0bbb09b2af9d ("soc: mediatek: SVS: add mt8192 SVS GPU driver") Signed-off-by: Roger Lu --- drivers/soc/mediatek/mtk-svs.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 0469c9dfeb04..2df30a6bca28 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1461,6 +1461,7 @@ static int svs_init02(struct svs_platform *svsp) { struct svs_bank *svsb; unsigned long flags, time_left; + int ret; u32 idx; for (idx = 0; idx < svsp->bank_max; idx++) { @@ -1479,7 +1480,8 @@ static int svs_init02(struct svs_platform *svsp) msecs_to_jiffies(5000)); if (!time_left) { dev_err(svsb->dev, "init02 completion timeout\n"); - return -EBUSY; + ret = -EBUSY; + goto out_of_init02; } } @@ -1497,12 +1499,30 @@ static int svs_init02(struct svs_platform *svsp) if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { if (svs_sync_bank_volts_from_opp(svsb)) { dev_err(svsb->dev, "sync volt fail\n"); - return -EPERM; + ret = -EPERM; + goto out_of_init02; } } } return 0; + +out_of_init02: + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + + spin_lock_irqsave(&svs_lock, flags); + svsp->pbank = svsb; + svs_switch_bank(svsp); + svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); + svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); + spin_unlock_irqrestore(&svs_lock, flags); + + svsb->phase = SVSB_PHASE_ERROR; + svs_adjust_pm_opp_volts(svsb); + } + + return ret; } static void svs_mon_mode(struct svs_platform *svsp)