From patchwork Tue Jan 10 18:58:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 41589 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2918207wrt; Tue, 10 Jan 2023 11:02:49 -0800 (PST) X-Google-Smtp-Source: AMrXdXsZPalRzUkPencXyJPu5M73VvOEFnwrUifvKp5pd53jFveFWXNOopgfGdQvjAur0A61eyDO X-Received: by 2002:a17:902:ed8c:b0:192:9022:87b4 with SMTP id e12-20020a170902ed8c00b00192902287b4mr44539354plj.40.1673377368774; Tue, 10 Jan 2023 11:02:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673377368; cv=none; d=google.com; s=arc-20160816; b=LANiqFPK+xUYqWM6bXdovTFFmY6wGfCgs4e5Ide+ccm/HZHzhCkbd1sbN47MGk2yYm PIWLSv3NHC1CjfV2a7Y0hvcx4w5OyYDW0hmhFuzkoF5BWr75vXO7LAcXdiHCRcaCWJsu TiTGZkLqzSr2gCwfoXZV/WMmsxaBOVH4pDexQCq+jX/q08puELtsVS+UGHONkBXblAaZ V2GSzntMqAcLa82aP+h5GHDNy4OXSGULRTRIyZaO0OtyW5ZZEJjjdchciKIrJeXbjQsl S6zriD+MACJRIhGfiyzrFOcDcJfG3PdNWQFIheIxF2+QxX9W0VL3vmrvhnESt7v9lhok 9K0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:reply-to:dkim-signature; bh=upUt0tkjVVo5kujG2THDyS9VuwSTirZ5ySsbyf+a2Vk=; b=MkEhBsArZMoBn/yDHds8siKa186ude3HDAVR/o7912lfDdlLKU99G/ruyGp3KxWx3v xwTWZLWEYU/x/v7Ib1EKLu5INdQPfbXkP36yd+I1mScwW6mjO7tmucDzkudy/VbQwksT 37OljldknZS+x1AJINIMToOv1/GSJqsMa2CxNhJkNVJ3hEiPpyspCEomgsbPhGyXWSJm plIgj56/K933Ri+Q2hCSwZwIyhs7k/S7QUk/DflE9BvM6xmX0bSype2iLy97gsEM/83o WaXBotB1zQTEneQwEFvIXF+7GFdBD854ST5fhmWjeedVl4ZBCIjqd/txSBqqSdfCczgF w2MA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20210112 header.b=TDmjeQs1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g7-20020a1709029f8700b00192a8d6e21csi11729436plq.458.2023.01.10.11.02.36; Tue, 10 Jan 2023 11:02:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20210112 header.b=TDmjeQs1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239447AbjAJS7N (ORCPT + 99 others); Tue, 10 Jan 2023 13:59:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239784AbjAJS6i (ORCPT ); Tue, 10 Jan 2023 13:58:38 -0500 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E63CC18E2F for ; Tue, 10 Jan 2023 10:58:31 -0800 (PST) Received: by mail-pj1-x104a.google.com with SMTP id h1-20020a17090a470100b0022646263abfso5258488pjg.6 for ; Tue, 10 Jan 2023 10:58:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=upUt0tkjVVo5kujG2THDyS9VuwSTirZ5ySsbyf+a2Vk=; b=TDmjeQs1Nx35Pnj9WFsSWVj6CGe4OuCAxxe9Uj2I0XxxteOWSUQ6lF/oPghE4q3D1E zLr973gqSe9z0IT9vS+MLR6tJHwSAReg7cX1R0FW9HzOmYqWOnnKZyG9AahfgNdgDw6S h6hq8qaNf1+r6Cr1qpROqlUJvqnhKvoWtp2O3jC9HoSUkRA/6IS0v1JCetsS+LSO2RRE M+8g4WfEY2Wp+9GCiMMWfWpZ5CNkBnaXtCVGULRsRLZg9MguZNelTRpUpFVODgGVBEG/ sxSvq2ZKnVgjntV7aDOe7nBsabkzLnN/4K7FYwOozz3+oGwXJgovNqB8/VtqFEGS7KTM ZZ2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=upUt0tkjVVo5kujG2THDyS9VuwSTirZ5ySsbyf+a2Vk=; b=JJVk64SFjQi+hW0Swmrvnz2ATTg5bNb5aQBIIhgOa6eHkUHLtDv69KqSZPZlMYEbgT foeqdhJNdntMhC2yf2aSiEOZzeD0+a0Rot0zLLpwKACgdiQ5AlIAOyN/puQnCgHLdmbt inufP/A/fXq1+lalRxmMOSdsj2438xQ6z1bV8EyMTb7TjQHsub9muK2B8DU2u6q7FJjx pANvEwNKnoJ1IDvtd7aurtU2HrfTKoFwqJ/UuiWKPbpp3GOzpCcSB2/ejguE3o58ax+t RTc8jcSbvW7u+MR+oY9+PrRAybZWNRv2/fQ8kHpVHfQCoWRM+m9woYynxjrsT9EazX0E CzJQ== X-Gm-Message-State: AFqh2kpx4kP2GQAt2lTDU5DYSTMlDX2MMwQB4GITsf5HAoEOtc393O1/ q6wgx+RRowKjnW/nigXuD3LbWUSOf57W X-Received: from mizhang-super.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1071]) (user=mizhang job=sendgmr) by 2002:a17:90a:d350:b0:223:fa07:7bfb with SMTP id i16-20020a17090ad35000b00223fa077bfbmr5690650pjx.38.1673377111533; Tue, 10 Jan 2023 10:58:31 -0800 (PST) Reply-To: Mingwei Zhang Date: Tue, 10 Jan 2023 18:58:22 +0000 In-Reply-To: <20230110185823.1856951-1-mizhang@google.com> Mime-Version: 1.0 References: <20230110185823.1856951-1-mizhang@google.com> X-Mailer: git-send-email 2.39.0.314.g84b9a713c41-goog Message-ID: <20230110185823.1856951-4-mizhang@google.com> Subject: [PATCH 3/4] KVM: selftests: x86: Enable checking on xcomp_bv in amx_test From: Mingwei Zhang To: kvm@vger.kernel.org Cc: linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Venkatesh Srinivas , Aaron Lewis , Mingwei Zhang X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754663347727760039?= X-GMAIL-MSGID: =?utf-8?q?1754663347727760039?= After tilerelease instruction, AMX tiles are in INIT state. According to Intel SDM vol 1. 13.10: "If RFBM[i] = 1, XSTATE_BV[i] is set to the value of XINUSE[i].", XSTATE_BV[18] should be cleared after xsavec. On the other hand, according to Intel SDM vol 1. 13.4.3: "If XCOMP_BV[i] = 1, state component i is located at a byte offset locationI from the base address of the XSAVE area". Since at the time of xsavec, XCR0[18] is set indicating AMX tile data component is still enabled, xcomp_bv[18] should be set. Complete the checks by adding the assert to xcomp_bv[18] after xsavec. Signed-off-by: Mingwei Zhang --- tools/testing/selftests/kvm/x86_64/amx_test.c | 30 +++++++++++++++++-- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/amx_test.c b/tools/testing/selftests/kvm/x86_64/amx_test.c index b2369f956fea..18203e399e9d 100644 --- a/tools/testing/selftests/kvm/x86_64/amx_test.c +++ b/tools/testing/selftests/kvm/x86_64/amx_test.c @@ -41,6 +41,12 @@ #define XSAVE_HDR_OFFSET 512 +struct xstate_header { + u64 xfeatures; + u64 xcomp_bv; + u64 reserved[6]; +} __packed; + struct xsave_data { u8 area[XSAVE_SIZE]; } __aligned(64); @@ -160,12 +166,26 @@ static void set_tilecfg(struct tile_config *cfg) static void set_xstatebv(void *data, uint64_t bv) { - *(uint64_t *)(data + XSAVE_HDR_OFFSET) = bv; + struct xstate_header *header = + (struct xstate_header *)(data + XSAVE_HDR_OFFSET); + + header->xfeatures = bv; } static u64 get_xstatebv(void *data) { - return *(u64 *)(data + XSAVE_HDR_OFFSET); + struct xstate_header *header = + (struct xstate_header *)(data + XSAVE_HDR_OFFSET); + + return header->xfeatures; +} + +static u64 get_xcompbv(void *data) +{ + struct xstate_header *header = + (struct xstate_header *)(data + XSAVE_HDR_OFFSET); + + return header->xcomp_bv; } static void init_regs(void) @@ -204,10 +224,14 @@ static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg, GUEST_SYNC(4); __tilerelease(); GUEST_SYNC(5); - /* bit 18 not in the XSTATE_BV after xsavec() */ + /* + * After xsavec() bit 18 is cleared in the XSTATE_BV but is set in + * the XCOMP_BV. + */ set_xstatebv(xsave_data, XFEATURE_MASK_XTILEDATA); __xsavec(xsave_data, XFEATURE_MASK_XTILEDATA); GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILEDATA) == 0); + GUEST_ASSERT((get_xcompbv(xsave_data) & XFEATURE_MASK_XTILEDATA) == XFEATURE_MASK_XTILEDATA); /* xfd=0x40000, disable amx tiledata */ wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILEDATA);