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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n64-20020a632743000000b00489a4cba34fsi11265148pgn.21.2023.01.09.23.26.30; Mon, 09 Jan 2023 23:26:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237458AbjAJHZg (ORCPT + 99 others); Tue, 10 Jan 2023 02:25:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237397AbjAJHZD (ORCPT ); Tue, 10 Jan 2023 02:25:03 -0500 Received: from 1wt.eu (wtarreau.pck.nerim.net [62.212.114.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B95AC496CF for ; Mon, 9 Jan 2023 23:24:58 -0800 (PST) Received: (from willy@localhost) by pcw.home.local (8.15.2/8.15.2/Submit) id 30A7Obee003929; Tue, 10 Jan 2023 08:24:37 +0100 From: Willy Tarreau To: "Paul E. McKenney" Cc: linux-kernel@vger.kernel.org, Willy Tarreau Subject: [PATCH v2 02/22] tools/nolibc: enable support for thumb1 mode for ARM Date: Tue, 10 Jan 2023 08:24:14 +0100 Message-Id: <20230110072434.3863-3-w@1wt.eu> X-Mailer: git-send-email 2.17.5 In-Reply-To: <20230110072434.3863-1-w@1wt.eu> References: <20230110072434.3863-1-w@1wt.eu> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754619555581981078?= X-GMAIL-MSGID: =?utf-8?q?1754619555581981078?= Passing -mthumb to the kernel.org arm toolchain failed to build because it defaults to armv5 hence thumb1, which has a fairly limited instruction set compared to thumb2 enabled with armv7 that is much more complete. It's not very difficult to adjust the instructions to also build on thumb1, it only adds a total of 3 instructions, so it's worth doing it at least to ease use by casual testers. It was verified that the adjusted code now builds and works fine for armv5, thumb1, armv7 and thumb2, as long as frame pointers are not used. Signed-off-by: Willy Tarreau --- tools/include/nolibc/arch-arm.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tools/include/nolibc/arch-arm.h b/tools/include/nolibc/arch-arm.h index 875b21975137..e4ba77b0310f 100644 --- a/tools/include/nolibc/arch-arm.h +++ b/tools/include/nolibc/arch-arm.h @@ -180,10 +180,16 @@ void __attribute__((weak,noreturn,optimize("omit-frame-pointer"))) _start(void) __asm__ volatile ( "pop {%r0}\n" // argc was in the stack "mov %r1, %sp\n" // argv = sp - "add %r2, %r1, %r0, lsl #2\n" // envp = argv + 4*argc ... - "add %r2, %r2, $4\n" // ... + 4 - "and %r3, %r1, $-8\n" // AAPCS : sp must be 8-byte aligned in the - "mov %sp, %r3\n" // callee, an bl doesn't push (lr=pc) + + "add %r2, %r0, $1\n" // envp = (argc + 1) ... + "lsl %r2, %r2, $2\n" // * 4 ... + "add %r2, %r2, %r1\n" // + argv + + "mov %r3, $8\n" // AAPCS : sp must be 8-byte aligned in the + "neg %r3, %r3\n" // callee, and bl doesn't push (lr=pc) + "and %r3, %r3, %r1\n" // so we do sp = r1(=sp) & r3(=-8); + "mov %sp, %r3\n" // + "bl main\n" // main() returns the status code, we'll exit with it. "movs r7, $1\n" // NR_exit == 1 "svc $0x00\n"