From patchwork Mon Jan 9 15:35:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashok Raj X-Patchwork-Id: 40946 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp2228267wrt; Mon, 9 Jan 2023 07:48:11 -0800 (PST) X-Google-Smtp-Source: AMrXdXsBDspxSGsaA0fn42jrxTCxz9kfnlfjUsXUO+TW34CtscfEEuElORCSBoP1fSJIW9t6gr35 X-Received: by 2002:a05:6402:3784:b0:46b:eadf:8d34 with SMTP id et4-20020a056402378400b0046beadf8d34mr53872366edb.7.1673279291338; Mon, 09 Jan 2023 07:48:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1673279291; cv=none; d=google.com; s=arc-20160816; b=Ueiq8+iRvGM8GHaGc+DSw2ZgweCzNSFBQrYGMr2tD7DjaM20WuRAYjaLEOQbBinBqE f5Pw+w3nduYoE1z1yGOTwXuR2dw+oCSLexYaxt3jHT8YdXOQnEUf06KLt0TtNXk93ADi Cf3nFJDCgOtR/wxNuamhMzw59cn1rAG9Dk8jl8wBYjrkdlORyJNFo6t4gqSJRSlbCkNV HnWpKPMS/brQLFAZinbCwTZlvGyD+ftqqJ6LWTuXWuexFf2pZBB1U2BtJI9aInCvvFcL 73h/aYddE9kZJMV3d/yd6CLJ1XnvBRrl3vCYd4a6DFN2sv3vU+Lut2+s/lN6AqbuszjI IyAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wEiwU9Wnk/Vk4JOxRHWZTXVKixaAtPtNoIC1UcELYHk=; b=m2JTw7tpfpG01UkLesJXbE9gknU3iq1FetNZe/lq+QiMoIzbnMRQ6TUcPh/fZfkDeA AQCoGDNxHKzlb7PlECC95SqPFBGrhsgyg33fzo5gqDOjugg/B7wFDENI3F7V8QIOtR4Y aIQGjzmJEJf21UVzVrtiDOauvzwyPx65uVqNn8oPxypGxecDXWztSXYMS+c99cU4Dt0l C0rqH7u0qdMjioWh6IoGgrKyRSsE0ELAseBbMFmiT1sQZ1OY2UefePTBuS1YJAUUKRJZ exJCFjgXNGyabLQ9rupMDnnh+vnLZwsVx3mf1QpXXPhVN7O3WrVNWUbxEP4n3gyX7PUj YYew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=i82XtK2o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s4-20020a17090699c400b007c16e4d5e9esi10103984ejn.412.2023.01.09.07.47.47; Mon, 09 Jan 2023 07:48:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=i82XtK2o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234538AbjAIPlK (ORCPT + 99 others); Mon, 9 Jan 2023 10:41:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234001AbjAIPkS (ORCPT ); Mon, 9 Jan 2023 10:40:18 -0500 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32F3E40C00 for ; Mon, 9 Jan 2023 07:36:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673278579; x=1704814579; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xdjl9pGXxNvh2LhHThzo3G8n2sH1qvrqMnZU/btrLb0=; b=i82XtK2o/0GM5i1XNjEqUYQhRuKzn+PP5xyI8y5vYIQeb06KtbsJE0Hq +gmplA3IT9L55O+pDWuXdHqLCuCr4fTuSYuCrlHLi+cPwjhbJIhwWUhpF 7ISmD+PJ87uLsK8E2CHgOCQ1kA87Ix7UdVPsR8Yezpgl+0KTQyFxGvF/V 4fTYxI8L3CF0a1p9BQeTLXeh1AzulZ3GqW5aVHwnQBnFcRC7wmUl1cOEQ e1X/2W+MrGdSF1FgxqsbNgWPP0ql1gVL3WnJwSdCgBwWd64hfMLYoLivU BLCeSJrFh6Y4oM0jFIhJ+3nWS7IDIs9OaCl0KjAlMRmes7o0WTzyY7mhj Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="385203585" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="385203585" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10585"; a="902023893" X-IronPort-AV: E=Sophos;i="5.96,311,1665471600"; d="scan'208";a="902023893" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2023 07:36:13 -0800 From: Ashok Raj To: Borislav Petkov , Thomas Gleixner Cc: X86-kernel , LKML Mailing List , Ashok Raj , Dave Hansen , Tony Luck , Ingo Molnar , alison.schofield@intel.com, reinette.chatre@intel.com, Tom Lendacky Subject: [PATCH v4 5/6] x86/microcode/intel: Print old and new rev during early boot Date: Mon, 9 Jan 2023 07:35:54 -0800 Message-Id: <20230109153555.4986-6-ashok.raj@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230109153555.4986-1-ashok.raj@intel.com> References: <20230109153555.4986-1-ashok.raj@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754560506095470404?= X-GMAIL-MSGID: =?utf-8?q?1754560506095470404?= Make early loading message to match late loading messages. Print both old and new revisions. This is helpful to know what the BIOS loaded revision is before an early update. New dmesg log is shown below. microcode: early update: 0x2b000041 -> 0x2b000070 date = 2000-01-01 Cache the early BIOS revision before the microcode update and change the print_ucode_info() so it prints both the old and new revision in the same format as microcode_reload_late(). Signed-off-by: Ashok Raj Reviewed-by: Thomas Gleixner Cc: LKML Cc: x86 Cc: Tony Luck Cc: Dave Hansen Cc: Alison Schofield Cc: Reinette Chatre Cc: Thomas Gleixner Cc: Tom Lendacky Cc: Ingo Molnar --- Updates since V1: Thomas: Commit log updates as suggested. --- arch/x86/kernel/cpu/microcode/intel.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 1d709b72cfd0..f24300830ed7 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -310,10 +310,10 @@ static bool load_builtin_intel_microcode(struct cpio_data *cp) /* * Print ucode update info. */ -static void print_ucode_info(unsigned int new_rev, unsigned int date) +static void print_ucode_info(int old_rev, int new_rev, unsigned int date) { - pr_info_once("microcode updated early to revision 0x%x, date = %04x-%02x-%02x\n", - new_rev, date & 0xffff, date >> 24, + pr_info_once("early update: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + old_rev, new_rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); } @@ -321,6 +321,7 @@ static void print_ucode_info(unsigned int new_rev, unsigned int date) static int delay_ucode_info; static int current_mc_date; +static int early_old_rev; /* * Print early updated ucode info after printk works. This is delayed info dump. @@ -331,7 +332,7 @@ void show_ucode_info_early(void) if (delay_ucode_info) { intel_cpu_collect_info(&uci); - print_ucode_info(uci.cpu_sig.rev. current_mc_date); + print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); delay_ucode_info = 0; } } @@ -340,30 +341,33 @@ void show_ucode_info_early(void) * At this point, we can not call printk() yet. Delay printing microcode info in * show_ucode_info_early() until printk() works. */ -static void print_ucode(int new_rev, int date) +static void print_ucode(int old_rev, int new_rev, int date) { struct microcode_intel *mc; int *delay_ucode_info_p; int *current_mc_date_p; + int *early_old_rev_p; delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); + early_old_rev_p = (int *)__pa_nodebug(&early_old_rev); *delay_ucode_info_p = 1; *current_mc_date_p = date; + *early_old_rev_p = old_rev; } #else -static inline void print_ucode(int new_rev, int date) +static inline void print_ucode(int old_rev, int new_rev, int date) { - print_ucode_info(new_rev, date); + print_ucode_info(old_rev, new_rev, date); } #endif static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) { struct microcode_intel *mc; - u32 rev; + u32 rev, old_rev; mc = uci->mc; if (!mc) @@ -389,6 +393,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); + old_rev = rev; rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) return -1; @@ -396,9 +401,9 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) uci->cpu_sig.rev = rev; if (early) - print_ucode(uci->cpu_sig.rev, mc->hdr.date); + print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); else - print_ucode_info(uci->cpu_sig.rev, mc->hdr.date); + print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); return 0; }