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Mon, 09 Jan 2023 15:44:28 +0100 From: Melissa Wen To: harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , alex.hung@amd.com, nicholas.kazlauskas@amd.com, sungjoon.kim@amd.com, seanpaul@chromium.org, bhawanpreet.lakha@amd.com, Shashank Sharma , ville.syrjala@linux.intel.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, kernel-dev@igalia.com, laurent.pinchart+renesas@ideasonboard.com, Melissa Wen , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 15/18] drm/amd/display: enable 3D-LUT DRM properties if supported Date: Mon, 9 Jan 2023 13:38:43 -0100 Message-Id: <20230109143846.1966301-16-mwen@igalia.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230109143846.1966301-1-mwen@igalia.com> References: <20230109143846.1966301-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754556803121561778?= X-GMAIL-MSGID: =?utf-8?q?1754556803121561778?= Enable DRM crtc properties related to 3D LUT resources (shaper LUT, 3D LUT and 3D LUT modes) if it's supported by DCN HW, that means DCN families 3.0+ Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 25 +++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 ++ 3 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index abbbb3813c1e..6f04719d0c1f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -786,6 +786,7 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); void amdgpu_dm_init_color_mod(void); int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); +void amdgpu_dm_enable_lut3d_prop(struct amdgpu_display_manager *dm, struct drm_crtc *crtc); int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct dc_plane_state *dc_plane_state); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 54d95745f0f0..c547957acd73 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -388,6 +388,31 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state) return 0; } +static bool has_mpc_lut3d_caps(struct amdgpu_display_manager *dm) +{ + return dm->dc->caps.color.mpc.num_3dluts ? true : false; +} + +/** + * amdgpu_dm_enable_lut3d_prop - enable 3D LUT DRM props if HW supports + * @crtc: DRM crtc + * @dm: amdgpu display manager + */ +void amdgpu_dm_enable_lut3d_prop(struct amdgpu_display_manager *dm, struct drm_crtc *crtc) +{ + int res; + + if (!has_mpc_lut3d_caps(dm)) + return; + + res = drm_crtc_create_lut3d_mode_property(crtc, amdgpu_lut3d_modes, + ARRAY_SIZE(amdgpu_lut3d_modes)); + if (res) + drm_dbg(crtc->dev, "CRTC init: Failed to create LUT 3D mode properties\n"); + + drm_crtc_enable_lut3d(crtc, MAX_COLOR_LUT_ENTRIES, true); +} + /** * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. * @crtc: amdgpu_dm crtc state diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 22125daf9dcf..96494f72a6f4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -461,6 +461,8 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, true, MAX_COLOR_LUT_ENTRIES); + amdgpu_dm_enable_lut3d_prop(dm, &acrtc->base); + drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); return 0;