From patchwork Fri Jan 6 05:50:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 39941 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp660030wrt; Thu, 5 Jan 2023 21:51:35 -0800 (PST) X-Google-Smtp-Source: AMrXdXtcuJ3Wl1iFo+eJ/xyc6uX8+xHyzjwQW1J7Nkzcx1AjXbgicIq5bvGyNIQFyky9eCAcaiUw X-Received: by 2002:a17:907:1710:b0:7c0:c36d:f5df with SMTP id le16-20020a170907171000b007c0c36df5dfmr58352752ejc.70.1672984294973; Thu, 05 Jan 2023 21:51:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1672984294; cv=pass; d=google.com; s=arc-20160816; b=SBIefhfGDQsWzmLnaaDfeKBfDIZea5PESVi9o2T/d4YKjg5lIXae+urFIoCukrQ8Fk kLpXRh394Pgxdx4smQ2YXq7tQ9KA0VzAf81zSslwmC967eyDo3QF0Ci+wRXCjnWD2kMd oLZ0Nj1MEC+FsLmJkimGmLjKSK3Khm68ePtXKm3sB9t3RJx+diQ6rKL0W4YbYjUwhjxo exlu0MK+VKGcDI4wvj4fYlod7AGjxwcgHrDeWPtp1zg7AzCWhwnZ5GQwTpQ3PMXi8tQf 6cRThxshs1aiwig/+eaj10iEZyVU2QHzOItpkyzpbl9VTeDU4b58Bdgs5u7+J4eEGfvZ DB8w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yoKWiOMYX/CHuiw6fIdemXv+XZyLuh38Xll8KW9TuBU=; b=dhlPTxIgyilICyu6FFlY2aDZwtjFglwqM+7CaohkjOP5Vhz8AUzq3N6XOLz6c3cdb2 JXI7hNouBxwi+8WMRXCts+oRjlMjNqHePzR6VS5ctANdPLoQJUdDviJbsMVA1xM+WWlL 1RdwxDdVd9EyrAO+7S8GtMnfh9F01xQwRCwugzjpZ/c4hkC15ko0HRXL/4g4TlGV6Phz SXlCyYzevQ345Bc0V1KjuAlQx+vVvzNvqIV/vvXfl90yUFVtI0s7dcTgVHRqW2Fyz4d+ YsffI/PrjHKRB+A98cI/Is5cN0SzqE8XF3MVIY8bIJfX+B3osuOL8IGbVXdiVUo7rnkP bf0w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=NZtIlzHH; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id dd10-20020a1709069b8a00b007c31599251csi312022ejc.590.2023.01.05.21.51.09; Thu, 05 Jan 2023 21:51:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=NZtIlzHH; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230407AbjAFFuP (ORCPT + 99 others); Fri, 6 Jan 2023 00:50:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229618AbjAFFuM (ORCPT ); Fri, 6 Jan 2023 00:50:12 -0500 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2073.outbound.protection.outlook.com [40.107.6.73]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67FD851304; Thu, 5 Jan 2023 21:50:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DfNBAc+Pxn1EfZXfFwI4K372t6hhnIJA7RLvwXpYq7bcUO6EGpk/SF4HS+pnjlfeW+54xWI1WxeI5plnXbCWLHVsHlcgjngCgYMAgzText4QeCV1Ww5NVsjyicadODolmcrJDuR78Op7J0NTQ2Uk4GScH41CsFB92iLl3VnHdZKuvyVk3VU72cWays5QNjMtXzAUUpIL++6ExH64eHpTOkCVTLNH64WxT4zXrQWKTELR8xt9c/3zHvIJqXOiCIb9c/rIJ3TZnhmb8d6BWeUfc8MoBLn1ckWqeo2pf9HZAegzDcKqeQ5XTE03sm1c5i7GzGzsc/N+Dek7b8Aq3CaneA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yoKWiOMYX/CHuiw6fIdemXv+XZyLuh38Xll8KW9TuBU=; b=DpvBb5dWjLl5przPjsFvz8E2RHAZgZHl2jjdzknDXc5E6KwLwAElZc7Rxu88tBzZJvuyQdcDin8h1bNntD1FeOPkJPpE0RJWTsu6cTNRBQwJCGv2GLqqBcHEpHRllt+GCA+4a/a9BHtkIbCXGMyi7Q4v3pVAu64FUiLrkiFyALRR/heys8DD1i92k2EK27Q+uX07t18CyjNODkFAitGzNmYOoVSb2izNqXapu7dZj1XTK7URTm7g1ULc/HqykYhN/pCzsj4dadoufbwTRFow5H5kGjbTcLySYlP1W5ouVCoup0BaAozq9ae/DcaqN+xGCjaKQatLmCeGbf+tHS4UBw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yoKWiOMYX/CHuiw6fIdemXv+XZyLuh38Xll8KW9TuBU=; b=NZtIlzHHFFAKfPd+pCPUc7iJwilqFizEqEvYsISAbZR7YEb1cqUVHuJQwC1qj0h0Irwe8Ow8KqwigyxLkphRotRQ0I0ABx0ziKkzEQVQbG4uffGrdQPrNK9WvYY3iYeYbAsRufYfozcCwOd94yyLaTXYf753XrRDLwv4fIbt0L8= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by PAXPR04MB8239.eurprd04.prod.outlook.com (2603:10a6:102:1c2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5944.19; Fri, 6 Jan 2023 05:50:07 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::5098:b45:626e:a5c1]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::5098:b45:626e:a5c1%7]) with mapi id 15.20.5944.019; Fri, 6 Jan 2023 05:50:07 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, guido.gunther@puri.sm, marcel.ziswiler@toradex.com, laurentiu.palcu@oss.nxp.com, robh@kernel.org Subject: [PATCH v14 1/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPU binding Date: Fri, 6 Jan 2023 13:50:51 +0800 Message-Id: <20230106055056.2883302-2-victor.liu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230106055056.2883302-1-victor.liu@nxp.com> References: <20230106055056.2883302-1-victor.liu@nxp.com> X-ClientProxiedBy: SGXP274CA0001.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b8::13) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|PAXPR04MB8239:EE_ X-MS-Office365-Filtering-Correlation-Id: 1748e388-e83f-4adc-81db-08daefa9ddaf X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nY4A1Eoahu0CfAn3w5CclOahJelOOUC+pNh9bkqE7SnE7JsxVQFjvic3urRTfKY+HW+8oVD/y1yZN5YSugsFy8dQkX66NSoWa1LtV+kVJJJXHYP3xwDoidbDEPnaKisqsff2pByDwWO21cdil3l0EPnUVygQ0fusksOcQGQPuwX3gHrqpONQ3Ii/y7QZ7lmymOqpC5m1B92q5e1UTH+BoYgbwgo3sw8CMVOP9znnR0eas2pDW5/cDp9jZZh1LirPgIsK0gJdyctz0s5Du/AdwAvdxWr31f/49NPzDgWNr8SoVPVraJAOOSyn3a2cMJHoZNwCcuNSrxTAMTK+CK4wXzm1XZgxyGuf5JIYllrnPDmyZJZTk7Ga8pLtLtp81wEwT/7nGPMJEO2MfYNf6pAgVHqOIvrdyuHj1Hh8PE+v010sEKFgXxzvdnO9PFF/OAcY/VZhN8cSoZJpikZR94X68bmIVShwNoZF6W0Sb6QE6rTKz9Tcchy7jF00J/lAzyBkrLpGCd/sFBJyM/me7v3+pmo39JzDAIHE7Rq5r9DOvW6soCEdLbjL0sSmi37mpmWPkkc+qpVI2NZg/8he9uYg0ZLOC4bQ/l5p05dUlrgyNimdjn2QQ0E8aKopKB+JMLKqGwARQhhx2qX0SQpN5fxf/D4fE0/04aQIP1Q+NZ5cWX2QJNMhvVyMqD6mpHOH65Su1mlNY0ZAvvJSEa9zec5j60GbMknKpriymAtYDQSrQIHGS3jKq7T9lA0PYwdYFMMr X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AM7PR04MB7046.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(346002)(366004)(396003)(376002)(136003)(39860400002)(451199015)(1076003)(83380400001)(186003)(26005)(2616005)(6506007)(86362001)(36756003)(38350700002)(38100700002)(6666004)(6512007)(8676002)(4326008)(7416002)(41300700001)(2906002)(5660300002)(8936002)(30864003)(478600001)(52116002)(966005)(66476007)(6486002)(66946007)(316002)(66556008);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wdxQ014G5yQm5cNpDJj8p5blXygqPwP1LIKveKrZGtS8tIW3Bb0e0254pL2QwC0tXEpW48NON1byD9ZeWYyMAxZ2ysPCJKmHrQ5vusYP/cbXyG17ZZyudyAcMCOQAMmIN9DkG1ecaYD27I7woLVhdeH7sTvPYmH5yXqQcH9DpMUCj94bu8udVR83J7X6H5TMDls6M55OE23hZsRP4Zsc1dFbcMFhV/KCbfPXD0mupVHJPzOqhSfV8WB4SCm7R7H48qm88b5DRANhxWf9F/dNyVBASsN5eDmsOzZVZZrgtTYBOwrVe+yfqnYMhm7PWDPJPr2nK4uI2dijIfPdvwVlLG3mKWPIEDP6fHiFGh8PWJ/MV9O2n26N+6t8/wQmaBKQm04GGy1Vxyc4dbzLlRotOfITAZhANKX30Yudq+mtPCYAtuzrN9/rY8xK0iQgDIBLDfpjiZd//Rj44kEIsLcLuiiDcU7uB1k/1NXt/tbHmSuVNTkjCzq9Rr8ae5i+67riKwgTUk6IiHbBGmYqJIYhH12Vpi9cMx8M6EnnMYMR0W+peVTtDou/Fgdlnz3lKEJfyfN7AJz60XNHxPb+9vTFbHh0WDW7opj/lK91aC2oGjXFGMWLqpNfzPOP+QAMaUZqVYAYU1e7ygAZX0dFRkf7dFyoLNYPq6zdm4QEu2Vk5w7VUBsXmtdR8AwQr4rm6RZDdoRntWGnLr0rUt6O7hcPJckGTYWUcO0xfK0MOJNmmPBciwB+U2w885huWt9kNLGDWkH1Aq0tt+ZhbDYG2vbv4Xuy9gtD7lHbSSzWM7Fkixa0ZWrDr6L4QKlZZ+MWIYcoAh3odi6aoiHEwh6r8JqHimW2LgsFYPFRZAnLEHetM9sv9gdqI32ZaUQPFryuNPYbT/eXIn2zSeMcdyAF0e1Ipk+9AVZ3fZst1UwTrNfnr5fINmhBwxslgMUVaBJKu7oM+fTeM4lc3eXwm9tz0y7XmwxnIIiPt66tm9rjZnhYaSSrgwDvoVjw+IpfnepInA2ivJVpFxZ6MpqCTAdXnkz3dy+6YZk3IHPPuC9Vv9sbJd+MWKqIvp7DTgWXfvhFx4sDBvKIhPd1Wjf0Vu9S04PV1IwhUoVWjDlsq+qcV8hl3pxKqfUyMYrGbQMssNbTeN1bEjiCqSmTb3SNb1a/MljuLI8fm3Gt7XGRss31YWzULY08WXgSRV1Un1fG1wVL0y2lFQdpWhLuVCulADltytjd495OUqXrmZUzcabjAYJ7OaiMM2935KGwUdK2XtgP5FRCbV/zLv0rzb398nMUqCkY3TNGBA8u5U5WiihA0aI1MZ8ZNEzVjWC5WiICQHkqpqJjhbxBBz95fMfqxe8LA432UPwy4h20fmXEVbXflfk3fc5B0ALbtYe4IAjw/yr10s2yc6/jHsBmhibCC+wW3yXio4/C6MXM8rNdUG3TEuzg3P4PkjKgcQBFQCH+U2zudl0gbdk5pzCpiOzRNUag7fAyeb/2Km5rioaifwsc/TtKeGUUgUwiWSGqD2e1Us5GhSG9xkSOV3ynB4MyhGp8Z7Wzj8IhhKD8H+9rLM978ni0zdUTaJNgcn5NE8lA/5Agiqp7 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1748e388-e83f-4adc-81db-08daefa9ddaf X-MS-Exchange-CrossTenant-AuthSource: AM7PR04MB7046.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2023 05:50:07.7405 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Hoov9eAsSbiHEL9e/HP447LRU6iqZqPCnQeNQrh9vAmCOd0jp/IlvHRUnl4kpDRM7vYMfd/rHEM3BvzMnd9MjQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8239 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754251180024013166?= X-GMAIL-MSGID: =?utf-8?q?1754251180024013166?= This patch adds bindings for i.MX8qxp/qm Display Processing Unit. Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- v7->v14: * No change. v6->v7: * Add Rob's R-b tag back. v5->v6: * Use graph schema. So, drop Rob's R-b tag as review is needed. v4->v5: * No change. v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag. v2->v3: * No change. v1->v2: * Fix yamllint warnings. * Require bypass0 and bypass1 clocks for both i.MX8qxp and i.MX8qm, as the display controller subsystem spec does say that they exist. * Use new dt binding way to add clocks in the example. * Trivial tweaks for the example. .../bindings/display/imx/fsl,imx8qxp-dpu.yaml | 387 ++++++++++++++++++ 1 file changed, 387 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml new file mode 100644 index 000000000000..6b05c586cd9d --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dpu.yaml @@ -0,0 +1,387 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Processing Unit + +maintainers: + - Liu Ying + +description: | + The Freescale i.MX8qm/qxp Display Processing Unit(DPU) is comprised of two + main components that include a blit engine for 2D graphics accelerations + and a display controller for display output processing, as well as a command + sequencer. + +properties: + compatible: + enum: + - fsl,imx8qxp-dpu + - fsl,imx8qm-dpu + + reg: + maxItems: 1 + + interrupts: + items: + - description: | + store9 shadow load interrupt(blit engine) + - description: | + store9 frame complete interrupt(blit engine) + - description: | + store9 sequence complete interrupt(blit engine) + - description: | + extdst0 shadow load interrupt + (display controller, content stream 0) + - description: | + extdst0 frame complete interrupt + (display controller, content stream 0) + - description: | + extdst0 sequence complete interrupt + (display controller, content stream 0) + - description: | + extdst4 shadow load interrupt + (display controller, safety stream 0) + - description: | + extdst4 frame complete interrupt + (display controller, safety stream 0) + - description: | + extdst4 sequence complete interrupt + (display controller, safety stream 0) + - description: | + extdst1 shadow load interrupt + (display controller, content stream 1) + - description: | + extdst1 frame complete interrupt + (display controller, content stream 1) + - description: | + extdst1 sequence complete interrupt + (display controller, content stream 1) + - description: | + extdst5 shadow load interrupt + (display controller, safety stream 1) + - description: | + extdst5 frame complete interrupt + (display controller, safety stream 1) + - description: | + extdst5 sequence complete interrupt + (display controller, safety stream 1) + - description: | + disengcfg0 shadow load interrupt + (display controller, display stream 0) + - description: | + disengcfg0 frame complete interrupt + (display controller, display stream 0) + - description: | + disengcfg0 sequence complete interrupt + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt0 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt1 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt2 + (display controller, display stream 0) + - description: | + framegen0 programmable interrupt3 + (display controller, display stream 0) + - description: | + signature0 shadow load interrupt + (display controller, display stream 0) + - description: | + signature0 measurement valid interrupt + (display controller, display stream 0) + - description: | + signature0 error condition interrupt + (display controller, display stream 0) + - description: | + disengcfg1 shadow load interrupt + (display controller, display stream 1) + - description: | + disengcfg1 frame complete interrupt + (display controller, display stream 1) + - description: | + disengcfg1 sequence complete interrupt + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt0 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt1 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt2 + (display controller, display stream 1) + - description: | + framegen1 programmable interrupt3 + (display controller, display stream 1) + - description: | + signature1 shadow load interrupt + (display controller, display stream 1) + - description: | + signature1 measurement valid interrupt + (display controller, display stream 1) + - description: | + signature1 error condition interrupt + (display controller, display stream 1) + - description: | + command sequencer error condition interrupt(command sequencer) + - description: | + common control software interrupt0(common control) + - description: | + common control software interrupt1(common control) + - description: | + common control software interrupt2(common control) + - description: | + common control software interrupt3(common control) + - description: | + framegen0 synchronization status activated interrupt + (display controller, safety stream 0) + - description: | + framegen0 synchronization status deactivated interrupt + (display controller, safety stream 0) + - description: | + framegen0 synchronization status activated interrupt + (display controller, content stream 0) + - description: | + framegen0 synchronization status deactivated interrupt + (display controller, content stream 0) + - description: | + framegen1 synchronization status activated interrupt + (display controller, safety stream 1) + - description: | + framegen1 synchronization status deactivated interrupt + (display controller, safety stream 1) + - description: | + framegen1 synchronization status activated interrupt + (display controller, content stream 1) + - description: | + framegen1 synchronization status deactivated interrupt + (display controller, content stream 1) + + interrupt-names: + items: + - const: store9_shdload + - const: store9_framecomplete + - const: store9_seqcomplete + - const: extdst0_shdload + - const: extdst0_framecomplete + - const: extdst0_seqcomplete + - const: extdst4_shdload + - const: extdst4_framecomplete + - const: extdst4_seqcomplete + - const: extdst1_shdload + - const: extdst1_framecomplete + - const: extdst1_seqcomplete + - const: extdst5_shdload + - const: extdst5_framecomplete + - const: extdst5_seqcomplete + - const: disengcfg_shdload0 + - const: disengcfg_framecomplete0 + - const: disengcfg_seqcomplete0 + - const: framegen0_int0 + - const: framegen0_int1 + - const: framegen0_int2 + - const: framegen0_int3 + - const: sig0_shdload + - const: sig0_valid + - const: sig0_error + - const: disengcfg_shdload1 + - const: disengcfg_framecomplete1 + - const: disengcfg_seqcomplete1 + - const: framegen1_int0 + - const: framegen1_int1 + - const: framegen1_int2 + - const: framegen1_int3 + - const: sig1_shdload + - const: sig1_valid + - const: sig1_error + - const: cmdseq_error + - const: comctrl_sw0 + - const: comctrl_sw1 + - const: comctrl_sw2 + - const: comctrl_sw3 + - const: framegen0_primsync_on + - const: framegen0_primsync_off + - const: framegen0_secsync_on + - const: framegen0_secsync_off + - const: framegen1_primsync_on + - const: framegen1_primsync_off + - const: framegen1_secsync_on + - const: framegen1_secsync_off + + clocks: + maxItems: 8 + + clock-names: + items: + - const: axi + - const: cfg + - const: pll0 + - const: pll1 + - const: bypass0 + - const: bypass1 + - const: disp0 + - const: disp1 + + power-domains: + items: + - description: DC power-domain + - description: PLL0 power-domain + - description: PLL1 power-domain + + power-domain-names: + items: + - const: dc + - const: pll0 + - const: pll1 + + fsl,dpr-channels: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle which points to DPR channels associated with + this DPU instance. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The DPU output port node from display stream0. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: The DPU output port node from display stream1. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - power-domain-names + - fsl,dpr-channels + - ports + +additionalProperties: false + +examples: + - | + #include + #include + dpu@56180000 { + compatible = "fsl,imx8qxp-dpu"; + reg = <0x56180000 0x40000>; + interrupt-parent = <&dc0_irqsteer>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <0>, + <1>, <2>, <3>, <4>, + <82>, <83>, <84>, <85>, + <209>, <210>, <211>, <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&dc0_dpu_lpcg IMX_LPCG_CLK_5>, + <&dc0_dpu_lpcg IMX_LPCG_CLK_4>, + <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_0_VIDEO1 IMX_SC_PM_CLK_BYPASS>, + <&dc0_disp_lpcg IMX_LPCG_CLK_0>, + <&dc0_disp_lpcg IMX_LPCG_CLK_1>; + clock-names = "axi", "cfg", + "pll0", "pll1", "bypass0", "bypass1", + "disp0", "disp1"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, + <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, + <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, + <&dc0_dpr2_channel3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu0_disp0_pixel_combiner0_ch0: endpoint { + remote-endpoint = <&pixel_combiner0_ch0_dpu0_disp0>; + }; + }; + + port@1 { + reg = <1>; + dpu0_disp1_pixel_combiner0_ch1: endpoint { + remote-endpoint = <&pixel_combiner0_ch1_dpu0_disp1>; + }; + }; + }; + };