From patchwork Fri Jan 6 01:01:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 39856 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp574322wrt; Thu, 5 Jan 2023 17:07:59 -0800 (PST) X-Google-Smtp-Source: AMrXdXtmHwgRR9QbhRlALKKFZBEbclC9iDQkxQCSF/zl73hHcC0D/yk/LHibQHgodCZIfH8dj+QV X-Received: by 2002:a17:90a:e7c1:b0:226:23e4:fd9e with SMTP id kb1-20020a17090ae7c100b0022623e4fd9emr30002605pjb.18.1672967279583; Thu, 05 Jan 2023 17:07:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1672967279; cv=none; d=google.com; s=arc-20160816; b=ZpHVTkB60UH3uFyyytS9YHHzCVb6qUg8ZAbHbflggXrhMcpRoJflviz8YzyaJjFPnP qppcYwxIEdokJPwglyEBfmizj0o7DGnjFb/8hjWt1h7gBlPKRCOyg1LdOGIi34m/9e2e BXeAfz84dwR34l/YRFcDGpoTsBsJ1ygiNhVbmVCpRB4TvjfbIBshhTqfPAsc5i9sWNx/ xasBK4aTxEOV2OtS8o/Jztx9CwljV87h4n6bqsTCR20Ey36bjLX+IXiR05i4Qr5wcr0c MWokFiDKwKoYmLLkSj32znW0HmCvO+yqUEDw5yUSsNEctp29YoZxvzdv9bZLwJNW33rH siLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=54LTUO+rn/Ie60MTzlQTY65Ny4nmWRz6uGG53jf7WRc=; b=bccH5vaVqNI6Hmqcrp6mt6oFcO12XZlCVWSBt6CSwb6Cq6MlVOV61EZ1zhF2PFEmDX FwHw4N5pzUBMMd72y1pZai4nuEblYAhgA3imzAbrrvqXh0FL1+eymjk2Bg6BS9wjbsQu 5acJjWwIaVfJCHufnEkcGxQZv5WitjfhXpMPxINKHgFLDzvlE0BxIRsQV0LQBfb5GQGR 1htjyZIKTfn0B2UKJmgSjgWbhl2kKZmPKz/eio4mFLRLmK9EnKM+RTp3Bx7MAy/q+wC1 5TdR7KA7uSCGUlX48dqYG0GBZTCv0d0KmGS06fhtvrGke7aAZD1woWiEJNitW9ptepi4 rW6A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o6-20020a63e346000000b00478d39fcb3dsi40460240pgj.519.2023.01.05.17.07.47; Thu, 05 Jan 2023 17:07:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236549AbjAFBEI (ORCPT + 99 others); Thu, 5 Jan 2023 20:04:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236211AbjAFBDz (ORCPT ); Thu, 5 Jan 2023 20:03:55 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7272C6E427; Thu, 5 Jan 2023 17:03:54 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0D72B15DB; Thu, 5 Jan 2023 17:04:36 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C53793F23F; Thu, 5 Jan 2023 17:03:51 -0800 (PST) From: Andre Przywara To: Samuel Holland , Jernej Skrabec , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski Cc: Icenowy Zheng , =?utf-8?b?QW5kcsOhcyBTemVtesO2?= , Fabien Poussin , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi Date: Fri, 6 Jan 2023 01:01:53 +0000 Message-Id: <20230106010155.26868-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.5 In-Reply-To: <20230106010155.26868-1-andre.przywara@arm.com> References: <20230106010155.26868-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754233337963132836?= X-GMAIL-MSGID: =?utf-8?q?1754233337963132836?= The Allwinner T113-s SoC is apparently using the same (or at least a very similar) die as the D1/D1s, but replaces the single RISC-V core with two Arm Cortex-A7 cores. Since the D1 core .dtsi already describes all common peripherals, we just need a DT describing the ARM specific peripherals: the CPU cores, the Generic Timer, the GIC and the PMU. We include the core .dtsi directly from the riscv DT directory. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/sun8i-t113s.dtsi | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-t113s.dtsi diff --git a/arch/arm/boot/dts/sun8i-t113s.dtsi b/arch/arm/boot/dts/sun8i-t113s.dtsi new file mode 100644 index 0000000000000..804aa197a24f8 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-t113s.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +};