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Thu, 5 Jan 2023 11:37:42 -0600 From: Hamza Mahfooz To: CC: Hamza Mahfooz , Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , "Pan, Xinhui" , David Airlie , Daniel Vetter , David Zhang , Nicholas Kazlauskas , Alex Hung , Po Ting Chen , Shirish S , Robin Chen , Brian Chang , Camille Cho , Tom Chung , , Subject: [PATCH v2] drm/amd/display: fix PSR-SU/DSC interoperability support Date: Thu, 5 Jan 2023 12:38:08 -0500 Message-ID: <20230105173809.289367-1-hamza.mahfooz@amd.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000EE3F:EE_|DM8PR12MB5397:EE_ X-MS-Office365-Filtering-Correlation-Id: 35837f35-03bb-4d7a-5f34-08daef438d8c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fA23wUPRiReVAluhlS7ks0WrACFNg7bnCwqnkyXq1We9ZWzV0COdMd8BoQGZ3pG/sXOISZ7ZJtT2616oHk4GvAqhYoBilgk1V+Zuy0+V+my1yzUEGIdAugt5trYkPSeLAvzVggl0+vRE+2q75F0ykX41KxJr3I6Lb+yzOqkpzkDRNDVMyKd0n78pqnXi7WrmO0FrerXjsxgYmyyis1z0nmQ/hb6yNchD2XejE1wcxnnOe9U65dwDiEm4qgnjJoQEedtJg1d040fHaavwSjtEZyNDAFMn9jJGCLrD7fhXiR/Vk7Y9d1Y50+qfTX5HKWnlUhNZvTMS8Ak3MiQ3m+1xKsRHEuMDl6sb9xKsPOHeL3K5MfOAunjdEBgBPoX75eJnbpfZCpd8ESgUGFYG+3PYEHWYNQbiftH5WCG/Pq+dogIl1pyRN9oB9mo4klno9ldArchVZ4pS4g7VFwzwMBYjtzbtcMIODbVHEPt1B+CSeGCykOheVDPEXf7hM4YKu0wgN3PN7hdlZORDiew2ZFpdQvr7TyJ4gmyd/sPHP8Uv+KtPdGcMuiWcPP6RYb1CmIb0YDE6f65pMIcqgIOiR8OSOSjRe+dzY1Y8OXnSrl/b4OsZz0Iy8v4A0HzaGbeNopluwEMrZOeAafMQRKRVAp/ywW7M6O0GZpdfBXmshJLLV7P1a9EcM/7H/tAUcmohMkbDL0bCR7zp/ZrImzA2xgnaoRsiSMZtjb5KCCk1AbqKRYd0kcBif74+qFtIL/+tDd1jcdIJw0iHj/yX+v+C4PO0Sg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(346002)(39860400002)(451199015)(40470700004)(46966006)(36840700001)(70586007)(5660300002)(44832011)(8936002)(41300700001)(8676002)(4326008)(2906002)(70206006)(316002)(54906003)(6916009)(478600001)(2616005)(336012)(26005)(186003)(82310400005)(40480700001)(6666004)(16526019)(83380400001)(426003)(1076003)(47076005)(82740400003)(356005)(81166007)(86362001)(40460700003)(36756003)(36860700001)(16060500005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 17:37:44.2668 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35837f35-03bb-4d7a-5f34-08daef438d8c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5397 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754205473922374491?= X-GMAIL-MSGID: =?utf-8?q?1754205473922374491?= Currently, there are issues with enabling PSR-SU + DSC. This stems from the fact that DSC imposes a slice height on transmitted video data and we are not conforming to that slice height in PSR-SU regions. So, pass slice_height into su_y_granularity to feed the DSC slice height into PSR-SU code. Signed-off-by: Hamza Mahfooz --- v2: move code to modules/power. --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 3 ++ .../amd/display/modules/power/power_helpers.c | 35 +++++++++++++++++++ .../amd/display/modules/power/power_helpers.h | 3 ++ 3 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index 26291db0a3cf..872d06fe1436 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -122,6 +122,9 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) psr_config.allow_multi_disp_optimizations = (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); + if (!psr_su_set_y_granularity(dc, link, stream, &psr_config)) + return false; + ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); } diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index 9b5d9b2c9a6a..4d27ad9f7370 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -916,3 +916,38 @@ bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_s { return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal); } + +bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link, + struct dc_stream_state *stream, + struct psr_config *config) +{ + uint16_t pic_height; + uint8_t slice_height; + + if (!dc->caps.edp_dsc_support || + link->panel_config.dsc.disable_dsc_edp || + !link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || + !stream->timing.dsc_cfg.num_slices_v) + return true; + + pic_height = stream->timing.v_addressable + + stream->timing.v_border_top + stream->timing.v_border_bottom; + slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v; + + if (slice_height) { + if (config->su_y_granularity && + (slice_height % config->su_y_granularity)) { + WARN(1, + "%s: dsc: %d, slice_height: %d, num_slices_v: %d\n", + __func__, + stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported, + slice_height, + stream->timing.dsc_cfg.num_slices_v); + return false; + } + + config->su_y_granularity = slice_height; + } + + return true; +} diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h index 316452e9dbc9..bb16b37b83da 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h @@ -59,4 +59,7 @@ void mod_power_calc_psr_configs(struct psr_config *psr_config, const struct dc_stream_state *stream); bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream); +bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link, + struct dc_stream_state *stream, + struct psr_config *config); #endif /* MODULES_POWER_POWER_HELPERS_H_ */