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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g11-20020a056402090b00b00469dd6e394asi32265593edz.579.2023.01.03.03.33.36; Tue, 03 Jan 2023 03:34:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="u0jyPGc/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237524AbjACLan (ORCPT + 99 others); Tue, 3 Jan 2023 06:30:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237447AbjACL3o (ORCPT ); Tue, 3 Jan 2023 06:29:44 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E96F10060; Tue, 3 Jan 2023 03:29:37 -0800 (PST) X-UUID: ea8ec37d831044f1a372fe3a8ea97f79-20230103 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=9JeE+5LqZ6k4NifYeA8Fk9/IcVz1Gx3PLSu0PON7bng=; b=u0jyPGc/lAFqCi8QD3naz6wyStcVPMK9Z/FrTdfn2Cx+jP47NJfHxUZ8XUZ0pgLf6xu1F2luh371ttJcHAk3ikdITY5cKgAx4E5bi8gu0CPZ/Y0BHKlDxgEKcOQtsypvwjCvNLy50KvWS+yHz3XEbdZQrB17fRk4zz7Ywy0+J6U=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.16,REQID:c7663e6d-4eb0-4e74-9bbb-d8a300b5e91a,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.16,REQID:c7663e6d-4eb0-4e74-9bbb-d8a300b5e91a,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:09771b1,CLOUDID:84a48053-dd49-462e-a4be-2143a3ddc739,B ulkID:230103192931MEA2OUOW,BulkQuantity:1,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:40,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: ea8ec37d831044f1a372fe3a8ea97f79-20230103 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 727530901; Tue, 03 Jan 2023 19:29:28 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 3 Jan 2023 19:29:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 3 Jan 2023 19:29:28 +0800 From: Roger Lu To: Matthias Brugger , Enric Balletbo Serra , Kevin Hilman , Nicolas Boichat CC: Fan Chen , Roger Lu , Jia-wei Chang , , , , , , Subject: [PATCH v3 12/14] soc: mediatek: mtk-svs: restore default voltages when svs_init02() fail Date: Tue, 3 Jan 2023 19:29:23 +0800 Message-ID: <20230103112925.16554-13-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230103112925.16554-1-roger.lu@mediatek.com> References: <20230103112925.16554-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1754000933367769494?= X-GMAIL-MSGID: =?utf-8?q?1754000933367769494?= If svs init02 fail, it means we cannot rely on svs bank voltages anymore. We need to disable svs function and restore DVFS opp voltages back to the default voltages for making sure we have enough DVFS voltages. Signed-off-by: Roger Lu --- drivers/soc/mediatek/mtk-svs.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index f4382def9736..1b4798a9101c 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1495,6 +1495,7 @@ static int svs_init02(struct svs_platform *svsp) { struct svs_bank *svsb; unsigned long flags, time_left; + int ret; u32 idx; for (idx = 0; idx < svsp->bank_max; idx++) { @@ -1513,7 +1514,8 @@ static int svs_init02(struct svs_platform *svsp) msecs_to_jiffies(5000)); if (!time_left) { dev_err(svsb->dev, "init02 completion timeout\n"); - return -EBUSY; + ret = -EBUSY; + goto out_of_init02; } } @@ -1531,12 +1533,21 @@ static int svs_init02(struct svs_platform *svsp) if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { if (svs_sync_bank_volts_from_opp(svsb)) { dev_err(svsb->dev, "sync volt fail\n"); - return -EPERM; + ret = -EPERM; + goto out_of_init02; } } } return 0; + +out_of_init02: + for (idx = 0; idx < svsp->bank_max; idx++) { + svsb = &svsp->banks[idx]; + svs_bank_disable_and_restore_default_volts(svsp, svsb); + } + + return ret; } static void svs_mon_mode(struct svs_platform *svsp)