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[80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:01 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 08/11] clk: imx: gate2: add device tree support Date: Sat, 31 Dec 2022 11:47:33 +0100 Message-Id: <20221231104736.12635-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753726369060941520?= X-GMAIL-MSGID: =?utf-8?q?1753726369060941520?= The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-gate2.c | 86 +++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index f16c4019f402..b28150bf1ff6 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -12,9 +12,26 @@ #include #include #include +#include +#include #include #include "clk.h" +#define CLK_GATE2_CGR_DISABLED 0 +#define CLK_GATE2_CGR_RUN 1 +#define CLK_GATE2_CGR_RUN_WAIT 2 +#define CLK_GATE2_CGR_RUN_WAIT_STOP 3 +#define CLK_GATE2_CGR_MASK 3 + +#define CLK_GATE2_MAX_GROUPS 16 + +struct clk_gate2_group { + const char *name; + unsigned int share_count; +}; + +static struct clk_gate2_group clk_gate2_groups[CLK_GATE2_MAX_GROUPS]; + /** * DOC: basic gateable clock which can gate and ungate its output * @@ -175,3 +192,72 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, return hw; } EXPORT_SYMBOL_GPL(clk_hw_register_gate2); + +/** + * of_imx_gate2_clk_setup() - Setup function for imx low power gate + * clock + * @node: device node for the clock + */ +static void __init of_imx_gate2_clk_setup(struct device_node *node) +{ + void __iomem *reg; + u8 i, bit_idx = 0; + u8 cgr_val = CLK_GATE2_CGR_RUN_WAIT_STOP; + u8 cgr_mask = CLK_GATE2_CGR_MASK; + unsigned long flags = CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT; + u8 gate2_flags = 0; + unsigned int *share_count = NULL; + const char *name = node->name, *parent_name; + const char *str; + struct clk_hw *hw; + u32 val; + + reg = of_iomap(node, 0); + if (IS_ERR(reg)) { + pr_err("failed to get reg address for %pOFn\n", node); + return; + } + + if (!of_property_read_u32(node, "fsl,bit-shift", &val)) + bit_idx = val; + + if (of_clk_get_parent_count(node) != 1) { + pr_err("%pOFn must have 1 parent clock\n", node); + return; + } + + if (!of_property_read_string(node, "sharing-group", &str)) { + for (i = 0; clk_gate2_groups[i].name && + i < ARRAY_SIZE(clk_gate2_groups); i++) { + if (!strcmp(clk_gate2_groups[i].name, str)) { + share_count = &clk_gate2_groups[i].share_count; + break; + } + } + + if (i == ARRAY_SIZE(clk_gate2_groups)) { + pr_err("failed to get shared count for %pOFn\n", node); + return; + } + + if (!share_count) { + clk_gate2_groups[i].name = + kstrdup_const(str, GFP_KERNEL); + share_count = &clk_gate2_groups[i].share_count; + } + } + + parent_name = of_clk_get_parent_name(node, 0); + of_property_read_string(node, "clock-output-names", &name); + + hw = clk_hw_register_gate2(NULL, name, parent_name, flags, reg, bit_idx, + cgr_val, cgr_mask, gate2_flags, + &imx_ccm_lock, share_count); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + pr_debug("name: %s, parent: %s, enable-bit: %d, flags: 0x%lx, gate2_flags: 0x%x\n", + name, parent_name, bit_idx, flags, gate2_flags); +} +CLK_OF_DECLARE(fsl_imx8mn_gate2_clk, "fsl,imx8mn-low-power-gate-clock", + of_imx_gate2_clk_setup);