The patch adds support for imx8mn mux clocks to be initialized directly
from the device tree. Currently all i.MX mux clocks are initialized by
legacy code with hardwired parameters. This approach has generated setup
functions with unclear names:
git grep "#define imx_clk_hw_mux" drivers/clk/imx/clk.h
drivers/clk/imx/clk.h:#define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \
drivers/clk/imx/clk.h:#define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \
drivers/clk/imx/clk.h:#define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
drivers/clk/imx/clk.h:#define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \
drivers/clk/imx/clk.h:#define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
So, let's start with this specific clock driver and hope that other
variants can be handled in the future, causing the legacy code to be
removed.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-mux.c | 258 ++++++++++++++++++++++++++++++++++++++
2 files changed, 259 insertions(+)
create mode 100644 drivers/clk/imx/clk-mux.c
@@ -15,6 +15,7 @@ mxc-clk-objs += clk-gate.o
mxc-clk-objs += clk-gate2.o
mxc-clk-objs += clk-gate-93.o
mxc-clk-objs += clk-gate-exclusive.o
+mxc-clk-objs += clk-mux.o
mxc-clk-objs += clk-pfd.o
mxc-clk-objs += clk-pfdv2.o
mxc-clk-objs += clk-pllv1.o
new file mode 100644
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Amarula Solutions
+ *
+ * Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+
+#include "clk.h"
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#define to_clk_imx_mux(_hw) container_of(_hw, struct clk_imx_mux, hw)
+
+struct clk_imx_mux {
+ struct clk_hw hw;
+ struct imx_clk_reg reg;
+ u32 mask;
+ u8 shift;
+ u8 saved_parent;
+};
+
+static int imx_clk_mux_write(const struct imx_clk_reg *reg, u32 val)
+{
+ int ret = 0;
+
+ if (reg->base) {
+ writel(val, reg->base + reg->offset);
+ } else if (reg->regmap) {
+ ret = regmap_write(reg->regmap, reg->offset, val);
+ } else {
+ pr_err("memory address not set\n");
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+static int imx_clk_mux_read(const struct imx_clk_reg *reg, u32 *val)
+{
+ int ret = 0;
+
+ if (reg->base) {
+ *val = readl(reg->base + reg->offset);
+ } else if (reg->regmap) {
+ ret = regmap_read(reg->regmap, reg->offset, val);
+ } else {
+ pr_err("memory address not set\n");
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+static u8 imx_clk_mux_get_parent(struct clk_hw *hw)
+{
+
+ struct clk_imx_mux *mux = to_clk_imx_mux(hw);
+ int num_parents = clk_hw_get_num_parents(hw);
+ unsigned int val;
+ int ret;
+
+ ret = imx_clk_mux_read(&mux->reg, &val);
+ if (ret)
+ return ret;
+
+ val = (val >> mux->shift) && mux->mask;
+
+ if (val >= num_parents)
+ return -EINVAL;
+
+ return val;
+}
+
+static int imx_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_imx_mux *mux = to_clk_imx_mux(hw);
+ unsigned int val;
+ int ret;
+
+ ret = imx_clk_mux_read(&mux->reg, &val);
+ if (ret)
+ return ret;
+
+ val &= ~(mux->mask << mux->shift);
+ val |= index << mux->shift;
+ return imx_clk_mux_write(&mux->reg, val);
+}
+
+/**
+ * imx_clk_mux_save_context - Save the parent selcted in the mux
+ * @hw: pointer struct clk_hw
+ *
+ * Save the parent mux value.
+ */
+static int imx_clk_mux_save_context(struct clk_hw *hw)
+{
+ struct clk_imx_mux *mux = to_clk_imx_mux(hw);
+
+ mux->saved_parent = imx_clk_mux_get_parent(hw);
+ return 0;
+}
+
+/**
+ * imx_clk_mux_restore_context - Restore the parent in the mux
+ * @hw: pointer struct clk_hw
+ *
+ * Restore the saved parent mux value.
+ */
+static void imx_clk_mux_restore_context(struct clk_hw *hw)
+{
+ struct clk_imx_mux *mux = to_clk_imx_mux(hw);
+
+ imx_clk_mux_set_parent(hw, mux->saved_parent);
+}
+
+const struct clk_ops imx_clk_mux_ops = {
+ .get_parent = imx_clk_mux_get_parent,
+ .set_parent = imx_clk_mux_set_parent,
+ .determine_rate = __clk_mux_determine_rate,
+ .save_context = imx_clk_mux_save_context,
+ .restore_context = imx_clk_mux_restore_context,
+};
+
+static void imx_clk_hw_unregister_mux(struct clk_hw *hw)
+{
+ struct clk_imx_mux *mux = to_clk_imx_mux(hw);
+
+ clk_hw_unregister(hw);
+ kfree(mux);
+}
+
+static struct clk_hw *imx_clk_hw_register_mux(struct device_node *node,
+ const char *name,
+ const char * const *parent_names,
+ u8 num_parents,
+ unsigned long flags,
+ struct imx_clk_reg *reg, u8 shift,
+ u32 mask)
+{
+ struct clk_init_data init = { NULL };
+ struct clk_imx_mux *mux;
+ struct clk_hw *hw;
+
+ int ret;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.flags = flags;
+ init.ops = &imx_clk_mux_ops;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ /* struct clk_mux assignments */
+ memcpy(&mux->reg, reg, sizeof(*reg));
+ mux->hw.init = &init;
+
+ hw = &mux->hw;
+ ret = of_clk_hw_register(node, hw);
+ if (ret) {
+ kfree(mux);
+ return ERR_PTR(ret);
+ }
+
+ return hw;
+}
+
+/**
+ * of_imx_mux_clk_setup() - Setup function for imx mux clock
+ * @node: device node for the clock
+ */
+static void __init of_imx_mux_clk_setup(struct device_node *node)
+{
+ struct clk_hw *hw;
+ unsigned int num_parents;
+ const char **parent_names;
+ const char *name = node->name;
+ struct imx_clk_reg reg = {};
+ u32 shift = 0;
+ u32 flags = CLK_SET_RATE_NO_REPARENT;
+ u32 val;
+ u32 mask;
+
+ reg.regmap = syscon_regmap_lookup_by_phandle(node, "fsl,anatop");
+ if (!IS_ERR(reg.regmap)) {
+ if (of_property_read_u32_index(node, "fsl,anatop", 1, &val)) {
+ pr_err("missing register offset for %pOFn\n", node);
+ return;
+ }
+
+ reg.offset = val;
+ } else {
+ reg.base = of_iomap(node, 0);
+ if (IS_ERR(reg.base)) {
+ pr_err("failed to get register address for %pOFn\n",
+ node);
+ return;
+ }
+ }
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 2) {
+ pr_err("%pOFn must have parents\n", node);
+ return;
+ }
+
+ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
+ if (!parent_names)
+ return;
+
+ of_clk_parent_fill(node, parent_names, num_parents);
+
+ of_property_read_u32(node, "fsl,bit-shift", &shift);
+
+ if (of_property_read_bool(node, "fsl,is-critical"))
+ flags |= CLK_IS_CRITICAL;
+
+ if (of_property_read_bool(node, "fsl,ops-parent-enable"))
+ flags |= CLK_OPS_PARENT_ENABLE;
+
+ if (of_property_read_bool(node, "fsl,set-rate-parent"))
+ flags |= CLK_SET_RATE_PARENT;
+
+ /* Generate bit-mask based on parent info */
+ mask = num_parents - 1;
+ mask = (1 << fls(mask)) - 1;
+
+ of_property_read_string(node, "clock-output-names", &name);
+
+ hw = imx_clk_hw_register_mux(node, name, parent_names, num_parents,
+ flags, ®, shift, mask);
+ if (IS_ERR(hw))
+ goto free_parent_names;
+
+ if (of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw)) {
+ imx_clk_hw_unregister_mux(hw);
+ goto free_parent_names;
+ }
+
+ pr_debug("name: %s, offset: 0x%x, shift: %d, mask: 0x%x\n", name,
+ reg.offset, shift, mask);
+
+free_parent_names:
+ kfree(parent_names);
+}
+CLK_OF_DECLARE(fsl_imx8mn_mux_clk, "fsl,imx8mn-mux-clock",
+ of_imx_mux_clk_setup);