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[83.9.31.184]) by smtp.gmail.com with ESMTPSA id e16-20020ac24e10000000b004b4ea0f4e25sm3447970lfr.301.2022.12.30.05.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 05:50:50 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: qcom: sm8250: Sort audio hw nodes Date: Fri, 30 Dec 2022 14:50:44 +0100 Message-Id: <20221230135044.287874-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221230135044.287874-1-konrad.dybcio@linaro.org> References: <20221230135044.287874-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753647500437835273?= X-GMAIL-MSGID: =?utf-8?q?1753647500437835273?= Half of the audio hardware nodes were not sorted properly. Fix that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 142 +++++++++++++-------------- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dffce681d417..0b6a6a809503 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2214,77 +2214,6 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; - wsamacro: codec@3240000 { - compatible = "qcom,sm8250-lpass-wsa-macro"; - reg = <0 0x03240000 0 0x1000>; - clocks = <&audiocc LPASS_CDC_WSA_MCLK>, - <&audiocc LPASS_CDC_WSA_NPL>, - <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&aoncc LPASS_CDC_VA_MCLK>, - <&vamacro>; - clock-names = "mclk", - "npl", - "macro", - "dcodec", - "va", - "fsgen"; - - pinctrl-names = "default"; - pinctrl-0 = <&wsa_swr_active>; - - #clock-cells = <0>; - clock-frequency = <9600000>; - clock-output-names = "mclk"; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - swr0: soundwire-controller@3250000 { - compatible = "qcom,soundwire-v1.5.1"; - reg = <0 0x03250000 0 0x2000>; - interrupts = ; - clocks = <&wsamacro>; - clock-names = "iface"; - - qcom,din-ports = <2>; - qcom,dout-ports = <6>; - - qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; - qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; - qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; - qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; - - #sound-dai-cells = <1>; - #address-cells = <2>; - #size-cells = <0>; - status = "disabled"; - }; - - audiocc: clock-controller@3300000 { - compatible = "qcom,sm8250-lpass-audiocc"; - reg = <0 0x03300000 0 0x30000>; - #clock-cells = <1>; - clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - clock-names = "core", "audio", "bus"; - }; - - vamacro: codec@3370000 { - compatible = "qcom,sm8250-lpass-va-macro"; - reg = <0 0x03370000 0 0x1000>; - clocks = <&aoncc LPASS_CDC_VA_MCLK>, - <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; - clock-names = "mclk", "macro", "dcodec"; - - #clock-cells = <0>; - clock-frequency = <9600000>; - clock-output-names = "fsgen"; - #sound-dai-cells = <1>; - }; - rxmacro: rxmacro@3200000 { compatible = "qcom,sm8250-lpass-rx-macro"; reg = <0 0x03200000 0 0x1000>; @@ -2388,6 +2317,77 @@ swr2: soundwire-controller@3230000 { status = "disabled"; }; + wsamacro: codec@3240000 { + compatible = "qcom,sm8250-lpass-wsa-macro"; + reg = <0 0x03240000 0 0x1000>; + clocks = <&audiocc LPASS_CDC_WSA_MCLK>, + <&audiocc LPASS_CDC_WSA_NPL>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&aoncc LPASS_CDC_VA_MCLK>, + <&vamacro>; + clock-names = "mclk", + "npl", + "macro", + "dcodec", + "va", + "fsgen"; + + pinctrl-names = "default"; + pinctrl-0 = <&wsa_swr_active>; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + swr0: soundwire-controller@3250000 { + compatible = "qcom,soundwire-v1.5.1"; + reg = <0 0x03250000 0 0x2000>; + interrupts = ; + clocks = <&wsamacro>; + clock-names = "iface"; + + qcom,din-ports = <2>; + qcom,dout-ports = <6>; + + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + status = "disabled"; + }; + + audiocc: clock-controller@3300000 { + compatible = "qcom,sm8250-lpass-audiocc"; + reg = <0 0x03300000 0 0x30000>; + #clock-cells = <1>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio", "bus"; + }; + + vamacro: codec@3370000 { + compatible = "qcom,sm8250-lpass-va-macro"; + reg = <0 0x03370000 0 0x1000>; + clocks = <&aoncc LPASS_CDC_VA_MCLK>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "macro", "dcodec"; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + aoncc: clock-controller@3380000 { compatible = "qcom,sm8250-lpass-aoncc"; reg = <0 0x03380000 0 0x40000>;