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Wed, 28 Dec 2022 10:31:21 -0600 From: Mario Limonciello To: Javier Martinez Canillas , Alex Deucher , CC: Carlos Soriano Sanchez , , , "David Airlie" , Daniel Vetter , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v2 07/11] drm/amd: Request MES microcode during IP discovery Date: Wed, 28 Dec 2022 10:30:54 -0600 Message-ID: <20221228163102.468-8-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228163102.468-1-mario.limonciello@amd.com> References: <20221228163102.468-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT076:EE_|SA3PR12MB8023:EE_ X-MS-Office365-Filtering-Correlation-Id: 20ecc42e-6921-4f52-a02d-08dae8f0f5ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +cS+EC2EsuXFQ6e7fQ5293EYPIBj+ISFlPA4f4g4XJswJQo7ZE0M42Xl5pOPiHOAY0aoB2zgRGIbiGhJPnyHo4nLzqcPrrzVh/10e2XDHNl5V9LugSbbpZKfoLXkgU2HfRGMuOT3APoSmBLS68HYOvRqeVc4lfSXNvESvx1hKXY/nItvnheHXP9NrnYAz1xalL66l9KtB9B8SgaKHhaWiTTztQUjqKr6npCoI4gmtrc+I3y7IsHKCRbyFDjhgNWtVJFRmfRmSNrehNPzCx+2Uh9LLHBtHBz/oEGojXtcZJCH902XMwf4dcEW9yf9ySOvog4NHHBiri2Hq1MLOrRO4qYtO6WStmyjLlq2EECMd+bH8heI0XALy5A3cVwM6P/JQgsL5yYD77FxFqLFqsz8RSLbppvBzAVx+k8k8WXmx+WDqG7Mhv6ABk4t4oJZur9/w2SqK74+Iy7Ogbb/wYc8r9qF4C3J0hrLY9xCxBkvSzKeJ2oh3r3CA7+naVu7B99uXQOK58p2PQR5bNxqkrgE3oToCdO6kkVwidf5c31p1thMDUmF3pixtb2sBhBZbHIvlYaA5ot7WQZGt8831uiw2uATxIlRiPUL8AWEsEcH+yGurUZ4XcVg7BBSNt8zl9DyEGYCInn3DvmVtn+dghKe975Rx3m7Dtm27aXfvyWgp8yS92ihVi8s+plGBKtnRAVSgKgDJbeo0po2I5BKf2c1b5zXcQeQwsuWG8QqGN7shqM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(396003)(376002)(136003)(451199015)(40470700004)(36840700001)(46966006)(186003)(1076003)(336012)(16526019)(26005)(2616005)(83380400001)(478600001)(6666004)(36756003)(47076005)(40460700003)(82310400005)(426003)(7696005)(86362001)(36860700001)(356005)(8936002)(41300700001)(40480700001)(110136005)(316002)(2906002)(54906003)(82740400003)(70206006)(70586007)(5660300002)(4326008)(81166007)(8676002)(44832011)(36900700001);DIR:OUT;SFP:1101; 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Move the request for MES microcode into the IP discovery phase so that if it's not available, IP discovery will fail. Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 39 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 28 ------------- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 25 +----------- 3 files changed, 40 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 1c26a3a60394..479266ed2b7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -145,6 +145,19 @@ MODULE_FIRMWARE("amdgpu/vcn_4_0_0.bin"); MODULE_FIRMWARE("amdgpu/vcn_4_0_2.bin"); MODULE_FIRMWARE("amdgpu/vcn_4_0_4.bin"); +MODULE_FIRMWARE("amdgpu/navi10_mes.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin"); +MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes1.bin"); + +MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -2041,10 +2054,29 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) r = amdgpu_discovery_load_vcn_fw(adev, ucode_prefix); return r; } + +static int amdgpu_discovery_load_mes_fw(struct amdgpu_device *adev, + enum admgpu_mes_pipe pipe, + const char *ucode_prefix) +{ + char fw_name[40]; + + if (pipe == AMDGPU_MES_SCHED_PIPE) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", + ucode_prefix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", + ucode_prefix); + + return request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); } static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) { + char ucode_prefix[30]; + int pipe, r; + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); + switch (adev->ip_versions[GC_HWIP][0]) { case IP_VERSION(10, 1, 10): case IP_VERSION(10, 1, 1): @@ -2077,6 +2109,13 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) default: break; } + if (adev->enable_mes) { + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + r = amdgpu_discovery_load_mes_fw(adev, pipe, ucode_prefix); + if (r) + return r; + } + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c index 614394118a53..9faa9867b3c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c @@ -37,10 +37,6 @@ #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 -MODULE_FIRMWARE("amdgpu/navi10_mes.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin"); -MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes1.bin"); - static int mes_v10_1_hw_fini(void *handle); static int mes_v10_1_kiq_hw_init(struct amdgpu_device *adev); @@ -382,34 +378,10 @@ static const struct amdgpu_mes_funcs mes_v10_1_funcs = { static int mes_v10_1_init_microcode(struct amdgpu_device *adev, enum admgpu_mes_pipe pipe) { - const char *chip_name; - char fw_name[30]; int err; const struct mes_firmware_header_v1_0 *mes_hdr; struct amdgpu_firmware_info *info; - switch (adev->ip_versions[GC_HWIP][0]) { - case IP_VERSION(10, 1, 10): - chip_name = "navi10"; - break; - case IP_VERSION(10, 3, 0): - chip_name = "sienna_cichlid"; - break; - default: - BUG(); - } - - if (pipe == AMDGPU_MES_SCHED_PIPE) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", - chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", - chip_name); - - err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); - if (err) - return err; - err = amdgpu_ucode_validate(adev->mes.fw[pipe]); if (err) { release_firmware(adev->mes.fw[pipe]); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 970b066b37bb..27176a1259ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -32,15 +32,6 @@ #include "v11_structs.h" #include "mes_v11_api_def.h" -MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); - static int mes_v11_0_hw_fini(void *handle); static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); @@ -462,25 +453,11 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = { static int mes_v11_0_init_microcode(struct amdgpu_device *adev, enum admgpu_mes_pipe pipe) { - char fw_name[30]; - char ucode_prefix[30]; + int err; const struct mes_firmware_header_v1_0 *mes_hdr; struct amdgpu_firmware_info *info; - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); - - if (pipe == AMDGPU_MES_SCHED_PIPE) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", - ucode_prefix); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", - ucode_prefix); - - err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); - if (err) - return err; - err = amdgpu_ucode_validate(adev->mes.fw[pipe]); if (err) { release_firmware(adev->mes.fw[pipe]);