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Wed, 28 Dec 2022 10:31:25 -0600 From: Mario Limonciello To: Javier Martinez Canillas , Alex Deucher , CC: Carlos Soriano Sanchez , , , "David Airlie" , Daniel Vetter , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v2 10/11] drm/amd: Request GFX11 microcode during IP discovery Date: Wed, 28 Dec 2022 10:30:57 -0600 Message-ID: <20221228163102.468-11-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228163102.468-1-mario.limonciello@amd.com> References: <20221228163102.468-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT076:EE_|DM4PR12MB5088:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d7340c1-6cca-4cca-5bda-08dae8f0f7d7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rQaMJnCW/zx+I+vDlgrxFUsfeoeHUwr7Zi0vRgcmVQvOlFlOzGsjeTaRf/zIty2F+u+8lGgd+t5kMDdxPPKWlS667Leg/8Ppfd0u14jfPrbI8dhj+4loIRI3A0Q2ZEpV2nufMOpBuY4bD2KY+fZE2O6O7u1cCh2Vpu7+FQwatiVCjkaNFKiFstdHdhimJk24rjJcaaPqZ8Ly/yL4nOKu+aZ3uxEqGi0vMeou/AvEFMDiiEg4+y+lvLFrs/lTz5Zzu8WLWrh38nFRjAgmC158FQgpZ4EedLIddy8kHYr/i3ka8qsqwmto3JGIKFCDUTeXXY4YLgCfpGMitLs9dKDzcUaOI9sLBdTO91JqaAhGsWTjA2FA3hPiV7xo9Mz75zc36GlwBK5yxS8eqxLxuM94ZyigQU2zu9siq1BD/c09/syueb9316Kq1St3j+xzAimACPeBHrQ9NpQjA1EZZlPfB2SbfFMY2BRV2XcItwtCLHMJ0OcbH+Tlo721Fr2hXuu/YICTc48xMnBLd5q/auWXEXelpOfik6tdIir7kKvSEYPUTb/+ayQyHBXw3DRAy1IGvXJLScpaT3h9zPUo2m7E2kzulKe48x3NZ46VmShOzMsDH47IleSMZStSI8Sd5RD1g2ElYetN9yJI71yYmytmWt+OEo7Ii3z3mAVBcyQme0QIYFIdn9myH1l2nChibEvwDGXE7L1kj5/H41AURn/xZ6ZWdbeUZdoPjAgdqp84ShQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(39860400002)(346002)(376002)(451199015)(36840700001)(46966006)(40470700004)(356005)(82740400003)(83380400001)(70586007)(81166007)(4326008)(8676002)(86362001)(316002)(70206006)(54906003)(36860700001)(41300700001)(40460700003)(19627235002)(40480700001)(2906002)(8936002)(5660300002)(1076003)(44832011)(2616005)(82310400005)(26005)(16526019)(186003)(336012)(426003)(478600001)(47076005)(6666004)(7696005)(110136005)(36756003)(36900700001);DIR:OUT;SFP:1101; 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Move the request for GFX11 microcode into the IP discovery phase so that if it's not available, IP discovery will fail. Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 52 +++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 64 +------------------ 2 files changed, 53 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index d31559600cae..c8c538a768fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -316,6 +316,29 @@ MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); +/* gfx11 */ +MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -2111,6 +2134,32 @@ static int amdgpu_discovery_load_gfx10(struct amdgpu_device *adev, char *ucode_p r = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); if (r) return r; + return 0; +} + +static int amdgpu_discovery_load_gfx11(struct amdgpu_device *adev, char *ucode_prefix) +{ + char fw_name[40]; + int r; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); + r = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (r) + return r; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); + r = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (r) + return r; + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); + r = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (r) + return r; + if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); + r = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); + if (r) + return r; + } return 0; } @@ -2159,6 +2208,9 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 3): case IP_VERSION(11, 0, 4): + r = amdgpu_discovery_load_gfx11(adev, ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index a56c6e106d00..576fa591c6da 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -60,27 +60,6 @@ #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX 1 -MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); -MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = { @@ -445,8 +424,6 @@ static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) { - char fw_name[40]; - char ucode_prefix[30]; int err; const struct rlc_firmware_header_v2_0 *rlc_hdr; uint16_t version_major; @@ -454,12 +431,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) DRM_DEBUG("\n"); - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.pfp_fw); if (err) goto out; @@ -476,10 +447,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.me_fw); if (err) goto out; @@ -492,10 +459,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) } if (!amdgpu_sriov_vf(adev)) { - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.rlc_fw); if (err) goto out; @@ -507,10 +470,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) goto out; } - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; err = amdgpu_ucode_validate(adev->gfx.mec_fw); if (err) goto out; @@ -530,9 +489,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) out: if (err) { - dev_err(adev->dev, - "gfx11: Failed to init firmware \"%s\"\n", - fw_name); + dev_err(adev->dev, "gfx11: Failed to init firmware\n"); release_firmware(adev->gfx.pfp_fw); adev->gfx.pfp_fw = NULL; release_firmware(adev->gfx.me_fw); @@ -549,20 +506,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) { const struct psp_firmware_header_v1_0 *toc_hdr; - int err = 0; - char fw_name[40]; - char ucode_prefix[30]; - - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); - err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); - if (err) - goto out; - - err = amdgpu_ucode_validate(adev->psp.toc_fw); - if (err) - goto out; toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); @@ -571,11 +514,6 @@ static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) adev->psp.toc.start_addr = (uint8_t *)toc_hdr + le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); return 0; -out: - dev_err(adev->dev, "Failed to load TOC microcode\n"); - release_firmware(adev->psp.toc_fw); - adev->psp.toc_fw = NULL; - return err; } static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev)