Message ID | 20221228113454.1199118-1-rodrigo.vivi@intel.com |
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x86/rapl: Treat Tigerlake like Icelake
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Commit Message
Rodrigo Vivi
Dec. 28, 2022, 11:34 a.m. UTC
From: Chris Wilson <chris@chris-wilson.co.uk> Since Tigerlake seems to have inherited its cstates and other rapl power caps from Icelake, assume it also follows Icelake for its rapl events. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- Based on the recent additions it looks like Tigerlake was a missed case in these events/rapl.c and that this old patch from Chris is the right way to go. I found this patch on our drm-intel's topic/core-for-CI branch while rebasing it towards v6.2-rc1. arch/x86/events/rapl.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index a829492bca4c..ae5779ea4417 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -800,6 +800,8 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = { X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &model_hsx), X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, &model_skl), + X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &model_skl), + X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &model_skl), X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, &model_skl),