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[2620:137:e000::1:20]) by mx.google.com with ESMTP id fy15-20020a1709069f0f00b0083c6206463asi1624587ejc.919.2022.12.22.23.41.48; Thu, 22 Dec 2022 23:42:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=PFeD+Mg4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230024AbiLWHgY (ORCPT + 99 others); Fri, 23 Dec 2022 02:36:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229637AbiLWHgW (ORCPT ); Fri, 23 Dec 2022 02:36:22 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DA52E5; Thu, 22 Dec 2022 23:36:20 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BN7a2w4130751; Fri, 23 Dec 2022 01:36:02 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1671780962; bh=i5R+eqtj2rYw1VP3DH7+6Q5MT0o6HnuZV6zjYYoleDo=; h=From:To:CC:Subject:Date; b=PFeD+Mg4nU+J3IHEivmL8wkJanLudEpY1kUwJQPSn9MTlsUGS6o602siUH5O+umDq vQ0PrUwOgIOSOeJ1VShHFF+hwOwjjGIw4pe1LDyYuzD5hM5Fc+XP6nGKI9FXFszCWT Le4ckm/vKmkovIRPCCePyhuMApHXS+vimwW4lAUc= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BN7a21v002899 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Dec 2022 01:36:02 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 23 Dec 2022 01:36:01 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 23 Dec 2022 01:36:01 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BN7a0MY019156; Fri, 23 Dec 2022 01:36:01 -0600 From: Bhavya Kapoor To: , CC: , , , , , Subject: [PATCH v3] arm64: dts: ti: k3-j721s2: Add support for ADC nodes Date: Fri, 23 Dec 2022 13:05:59 +0530 Message-ID: <20221223073559.109760-1-b-kapoor@ti.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752989782181331381?= X-GMAIL-MSGID: =?utf-8?q?1752989782181331381?= J721s2 has two instances of 8 channel ADCs in MCU domain. Add DT nodes for 8 channel ADCs for J721s2 SoC. Signed-off-by: Bhavya Kapoor --- Changelog v2->v3: - Added Newline at the end of files. .../dts/ti/k3-j721s2-common-proc-board.dts | 14 +++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 42 ++++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a7aa6cf08acd..3bc4f28c809f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -309,3 +309,17 @@ &mcu_mcan1 { pinctrl-0 = <&mcu_mcan1_pins_default>; phys = <&transceiver2>; }; + +&tscadc0 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 0af242aa9816..b99021927d2a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -306,4 +306,44 @@ cpts@3d000 { ti,cpts-periodic-outputs = <2>; }; }; -}; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x0 0x40200000 0x0 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am3359-tscadc"; + reg = <0x0 0x40210000 0x0 0x1000>; + interrupts = ; + power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 1 0>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + dmas = <&main_udmap 0x7402>, + <&main_udmap 0x7403>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + };