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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2022 16:04:15.6040 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62112302-1bcf-4901-e266-08dae2a3d7f3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8147 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752749709528304807?= X-GMAIL-MSGID: =?utf-8?q?1752749709528304807?= Adding support for dummy memory controller clients for use by software. --- drivers/memory/tegra/mc.c | 65 +++++++++++++++++++++++---------- drivers/memory/tegra/tegra234.c | 21 +++++++++++ include/soc/tegra/mc.h | 3 ++ include/soc/tegra/tegra-icc.h | 7 ++++ 4 files changed, 76 insertions(+), 20 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index ff887fb03bce..4ddf9808fe6b 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -755,6 +755,39 @@ const char *const tegra_mc_error_names[8] = { [6] = "SMMU translation error", }; +static int tegra_mc_add_icc_node(struct tegra_mc *mc, unsigned int id, const char *name, + unsigned int bpmp_id, unsigned int type) +{ + struct tegra_icc_node *tnode; + struct icc_node *node; + int err; + + tnode = kzalloc(sizeof(*tnode), GFP_KERNEL); + if (!tnode) + return -ENOMEM; + + /* create MC client node */ + node = icc_node_create(id); + if (IS_ERR(node)) + return -EINVAL; + + node->name = name; + icc_node_add(node, &mc->provider); + + /* link Memory Client to Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_MC); + if (err) + return err; + + node->data = tnode; + tnode->node = node; + tnode->bpmp_id = bpmp_id; + tnode->type = type; + tnode->mc = mc; + + return 0; +} + /* * Memory Controller (MC) has few Memory Clients that are issuing memory * bandwidth allocation requests to the MC interconnect provider. The MC @@ -780,7 +813,6 @@ const char *const tegra_mc_error_names[8] = { */ static int tegra_mc_interconnect_setup(struct tegra_mc *mc) { - struct tegra_icc_node *tnode; struct icc_node *node; unsigned int i; int err; @@ -820,30 +852,23 @@ static int tegra_mc_interconnect_setup(struct tegra_mc *mc) goto remove_nodes; for (i = 0; i < mc->soc->num_clients; i++) { - tnode = kzalloc(sizeof(*tnode), GFP_KERNEL); - if (!tnode) - return -ENOMEM; - - /* create MC client node */ - node = icc_node_create(mc->soc->clients[i].id); - if (IS_ERR(node)) { - err = PTR_ERR(node); + err = tegra_mc_add_icc_node(mc, mc->soc->clients[i].id, + mc->soc->clients[i].name, + mc->soc->clients[i].bpmp_id, + mc->soc->clients[i].type); + if (err) goto remove_nodes; - } - node->name = mc->soc->clients[i].name; - icc_node_add(node, &mc->provider); + } + + for (i = 0; i < mc->soc->num_sw_clients; i++) { + err = tegra_mc_add_icc_node(mc, mc->soc->sw_clients[i].id, + mc->soc->sw_clients[i].name, + mc->soc->sw_clients[i].bpmp_id, + mc->soc->sw_clients[i].type); - /* link Memory Client to Memory Controller */ - err = icc_link_create(node, TEGRA_ICC_MC); if (err) goto remove_nodes; - - node->data = tnode; - tnode->node = node; - tnode->type = mc->soc->clients[i].type; - tnode->bpmp_id = mc->soc->clients[i].bpmp_id; - tnode->mc = mc; } return 0; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 420546270c8b..82ce6c3c3eb0 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -780,6 +780,25 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { } }; +static const struct tegra_mc_sw_client tegra234_mc_sw_clients[] = { + { + .id = TEGRA_ICC_MC_CPU_CLUSTER0, + .name = "sw_cluster0", + .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA_ICC_MC_CPU_CLUSTER1, + .name = "sw_cluster1", + .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER1, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA_ICC_MC_CPU_CLUSTER2, + .name = "sw_cluster2", + .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2, + .type = TEGRA_ICC_NISO, + }, +}; + /* * tegra234_mc_icc_set() - Pass MC client info to External Memory Controller (EMC) * @src: ICC node for Memory Controller's (MC) Client @@ -854,6 +873,8 @@ static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = { const struct tegra_mc_soc tegra234_mc_soc = { .num_clients = ARRAY_SIZE(tegra234_mc_clients), .clients = tegra234_mc_clients, + .num_sw_clients = ARRAY_SIZE(tegra234_mc_sw_clients), + .sw_clients = tegra234_mc_sw_clients, .num_address_bits = 40, .num_channels = 16, .client_id_mask = 0x1ff, diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 0a32a9eb12a4..6a94e88b6100 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -192,6 +192,9 @@ struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; + const struct tegra_mc_sw_client *sw_clients; + unsigned int num_sw_clients; + const unsigned long *emem_regs; unsigned int num_emem_regs; diff --git a/include/soc/tegra/tegra-icc.h b/include/soc/tegra/tegra-icc.h index 3855d8571281..f9bcaae8ffee 100644 --- a/include/soc/tegra/tegra-icc.h +++ b/include/soc/tegra/tegra-icc.h @@ -22,6 +22,13 @@ struct tegra_icc_node { u32 type; }; +struct tegra_mc_sw_client { + unsigned int id; + unsigned int bpmp_id; + unsigned int type; + const char *name; +}; + /* ICC ID's for MC client's used in BPMP */ #define TEGRA_ICC_BPMP_DEBUG 1 #define TEGRA_ICC_BPMP_CPU_CLUSTER0 2