From patchwork Tue Dec 20 06:36:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 34916 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2813014wrn; Mon, 19 Dec 2022 23:02:43 -0800 (PST) X-Google-Smtp-Source: AA0mqf6tocX2pHe5bc225U3S8a/1v33fT9HqmR+OFpxiOqfAp3L/zL9su/cxYpJP3FF8rDI9bhaG X-Received: by 2002:aa7:814f:0:b0:566:900d:51d2 with SMTP id d15-20020aa7814f000000b00566900d51d2mr39958774pfn.1.1671519762925; Mon, 19 Dec 2022 23:02:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671519762; cv=none; d=google.com; s=arc-20160816; b=ynhM3I9QbX0iT3YJtHJVe3tvCg8BVlU8KNiGzMR1pbzxeva7ng9Th7G/hcz03uvcnR zEGYR89tN230kdgyR/Np76d/bfDaKXLnXyuof5FMjp1GuuN2Bm7Q1TUQfIbW0WDaBdgw u166GkMrsWn0+DIJZ6u9khBO5a4QZdFqB3+jI1kCfv4FFs4AOVJk8sggupnWopq1A6Sk LJQ3+/TCN9GjI3T0U0TcuKgR0cki2P5GiuT3yNG3udxh8TgcMy4rIbteRp4aQWr5TEjo pysZnkMMuVN2PQnGZ9icGuCB03hUuwEQgfIejftevreJizMDEBV5GmEVSAf8wg8Cijwx IsLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2LToYb8uS3nLyfTXZ/yWz0C8PFTjh6MmBnEKAPU6CiI=; b=Naha76MxysPM7kFj1xSmmOYhrTeSJOES4Xcuxm+cIJniI3+/RDCqEzd8gqjcrUrvoq zAKyGQOBd8RHc1BwwL0keSBPOUQheHmMWSBIW4lysFpX2jO18rdHqSABw8ImyqgHhFL0 sPH4DBZjWUWs13Fucm47/CMrcqPaUnEs+Z4y5jlUEjxJ3UQHLi/X5qcWcYVsNR1Wozbu MARo1ehDPLCpgbhG4k9AMHBigkc0CydXNqe5tHqVZl217atLILOo9ExWgWt0OujHzLfW ovXt0v5hNOR3Sy/Q2IODpVUqgtoNhsyHK9t2sEoH4LVNF75GIvS0gjmIszSB0F6tX+sP tfaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=PoBoDKCf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z10-20020a056a00240a00b0056282b4a984si13004877pfh.126.2022.12.19.23.02.30; Mon, 19 Dec 2022 23:02:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=PoBoDKCf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233367AbiLTHBz (ORCPT + 99 others); Tue, 20 Dec 2022 02:01:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232920AbiLTHBb (ORCPT ); Tue, 20 Dec 2022 02:01:31 -0500 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05AC1DEC6; Mon, 19 Dec 2022 23:01:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671519690; x=1703055690; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t538ktauL1cAgq6AUr7Ip99zqgMTE2CVEc4jgszwTWk=; b=PoBoDKCfIBPEZDfKN8E6HndXBXY4ahxuMMcR5ndmeNEE3PqSgc8Tz3tY pll2fsGdDfWW2aKx+0oQc7V5fT7fkQWeDN5OPzn0bvtYjRwhUNcGEuOel TiaZmsQ+GEdnQtwLtSfpMtY+I/i8lPPQQ29gC6yoMhlqUAWque54DSbdA WYmKKsjKtslfr1OTvwviNJAWNjRrZaIulE5ZmUfjH4iii5JOHaGBW7yyK Cj0uo4T0SxCp+tB1VSeKE+KBtBoxcrZWUIXwIKkkYlHpDp+zvYDCHSPia mJ8pihvlbR4mXfTr9XbGjSUVqdJUzaz3NGDClufqspXRKHayy3C79S3mt g==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="302971938" X-IronPort-AV: E=Sophos;i="5.96,258,1665471600"; d="scan'208";a="302971938" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 23:01:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="644326431" X-IronPort-AV: E=Sophos;i="5.96,258,1665471600"; d="scan'208";a="644326431" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga007.jf.intel.com with ESMTP; 19 Dec 2022 23:01:10 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [RFC PATCH 06/32] x86/cpufeature: add the cpu feature bit for FRED Date: Mon, 19 Dec 2022 22:36:32 -0800 Message-Id: <20221220063658.19271-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221220063658.19271-1-xin3.li@intel.com> References: <20221220063658.19271-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752715506942529478?= X-GMAIL-MSGID: =?utf-8?q?1752715506942529478?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for FRED (Flexible Return and Event Delivery). The Intel flexible return and event delivery (FRED) architecture defines simple new transitions that change privilege level (ring transitions). The FRED architecture was designed with the following goals: 1) Improve overall performance and response time by replacing event delivery through the interrupt descriptor table (IDT event delivery) and event return by the IRET instruction with lower latency transitions. 2) Improve software robustness by ensuring that event delivery establishes the full supervisor context and that event return establishes the full user context. The new transitions defined by the FRED architecture are FRED event delivery and, for returning from events, two FRED return instructions. FRED event delivery can effect a transition from ring 3 to ring 0, but it is used also to deliver events incident to ring 0. One FRED instruction (ERETU) effects a return from ring 0 to ring 3, while the other (ERETS) returns while remaining in ring 0. The Intel FRED architecture spec can be downloaded from: https://cdrdv2.intel.com/v1/dl/getContent/678938 Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 29f53b31056e..6148e8a94d24 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -312,6 +312,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ +#define X86_FEATURE_FRED (12*32+ 17) /* Flexible Return and Event Delivery */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index 3dc1a48c2796..41d1e1b4a6cb 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_FRED (12*32+ 17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */