From patchwork Tue Dec 20 00:55:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hal Feng X-Patchwork-Id: 34858 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp2701760wrn; Mon, 19 Dec 2022 16:56:19 -0800 (PST) X-Google-Smtp-Source: AA0mqf5vSwMbRRXpFc/185IBPQtP0q2264LkEcA+X4e0lt1lBlBIGrQUPVnH4KxExdEsYTozxQ0w X-Received: by 2002:a17:902:c3c3:b0:18d:6138:e4f6 with SMTP id j3-20020a170902c3c300b0018d6138e4f6mr46187894plj.29.1671497779622; Mon, 19 Dec 2022 16:56:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671497779; cv=none; d=google.com; s=arc-20160816; b=ze1Hq/BGoyfw/XGY2A85/4Y/hhlkea2q16mSaLMlRV9dBgiO8VuchraP9jsZVCxmm9 lKrzzdfI9Q42GbkEFEB3RzKOvJj9cUQWNSIXsMYZbqg4ziDvFU54SC5IVYN4m87bCi3M 6mJCJK8CC6skwc+qcGEeMQmcKei9RipFn4fiV1j5CPJZoi0zLL1WgNi6QMs6VtftpKWT fsw5PeWjbdgka+wmgdfm53gKsKTXM5jHx5G4+8H31WTAJoCFQpVXVtyIbQh1Af+OMwqm /Z0X3pUfsKOc0LiFyM/I+f6BogL2mWEzs/tvMhH6TbrZbdueVXfn3rIpKNghEwppNShh djeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=jzv3Yg2lMXVQGhSsdZSLJwTsUvE11aZ4LJOMC+3S6h0=; b=KBBjoOSSrhlad54eeUmG4oTGpu2NxM4z3ms4jA8njmWgPlpoMHiJZqgyoP/plDL0DN Cq8IniPmjlhadYs3ePK4yyWHn8UxtBV1L0K8bRY5mUPe60q5hlzVykdl/bx7hcXYwH+3 XBsIPD1kPa4QHx+j57onYut2zcRFAOj0bdsnHL9kbvraVE3Uxbax3/kzq6FCG5SCViCj Mfu2OolZgR26zs/5YHb4O2BEpR57uQtmrWlGLJfWhKExz1Gkk4Ua693WQ4Uf/R547U7R wLIwecEmDoYqj1E4c8UkntlzLyR+WV9CiSZDs28X5hqM2ZLYvV8H2/sHXWjqA0yATEAE RFXg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l15-20020a170902f68f00b00186c3727109si13629947plg.41.2022.12.19.16.56.06; Mon, 19 Dec 2022 16:56:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232982AbiLTAzr convert rfc822-to-8bit (ORCPT + 99 others); Mon, 19 Dec 2022 19:55:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232621AbiLTAzg (ORCPT ); Mon, 19 Dec 2022 19:55:36 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C30CE164B5; Mon, 19 Dec 2022 16:55:34 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 5BF1724DFD7; Tue, 20 Dec 2022 08:55:33 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 20 Dec 2022 08:55:33 +0800 Received: from ubuntu.localdomain (183.27.97.120) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 20 Dec 2022 08:55:32 +0800 From: Hal Feng To: , , CC: Conor Dooley , Palmer Dabbelt , "Rob Herring" , Krzysztof Kozlowski , Linus Walleij , Emil Renner Berthing , Jianlong Huang , Hal Feng , Subject: [PATCH v3 3/5] dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl Date: Tue, 20 Dec 2022 08:55:27 +0800 Message-ID: <20221220005529.34744-4-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221220005529.34744-1-hal.feng@starfivetech.com> References: <20221220005529.34744-1-hal.feng@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.120] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752692455422794980?= X-GMAIL-MSGID: =?utf-8?q?1752692455422794980?= From: Jianlong Huang Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller. Signed-off-by: Jianlong Huang Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng --- .../pinctrl/starfive,jh7110-aon-pinctrl.yaml | 126 ++++++++++++++++++ .../pinctrl/starfive,jh7110-pinctrl.h | 22 +++ 2 files changed, 148 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml new file mode 100644 index 000000000000..ff8098c31ecc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Aon Pin Controller + +description: | + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. + + Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO4 + can be multiplexed and have configurable bias, drive strength, + schmitt trigger etc. + Some peripherals have their I/O go through the 4 "GPIOs". This also + includes PWM. + +maintainers: + - Jianlong Huang + +properties: + compatible: + const: starfive,jh7110-aon-pinctrl + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +patternProperties: + '-[0-9]+$': + type: object + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, system signal configuration, pin groups for + vin/vout module, pin voltage, mux functions for output, mux functions + for output enable, mux functions for input. + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the GPIOMUX macro. + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pinmux + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + gpio@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x17020000 0x10000>; + resets = <&aoncrg 2>; + interrupts = <85>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + pwm-0 { + pwm-pins { + pinmux = <0xff030802>; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + }; + +... diff --git a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h index c97dde8e864c..bff3dafd5671 100644 --- a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h +++ b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h @@ -104,6 +104,28 @@ #define PAD_QSPI_DATA2 93 #define PAD_QSPI_DATA3 94 +/* aon_iomux pin */ +#define PAD_TESTEN 0 +#define PAD_RGPIO0 1 +#define PAD_RGPIO1 2 +#define PAD_RGPIO2 3 +#define PAD_RGPIO3 4 +#define PAD_RSTN 5 +#define PAD_GMAC0_MDC 6 +#define PAD_GMAC0_MDIO 7 +#define PAD_GMAC0_RXD0 8 +#define PAD_GMAC0_RXD1 9 +#define PAD_GMAC0_RXD2 10 +#define PAD_GMAC0_RXD3 11 +#define PAD_GMAC0_RXDV 12 +#define PAD_GMAC0_RXC 13 +#define PAD_GMAC0_TXD0 14 +#define PAD_GMAC0_TXD1 15 +#define PAD_GMAC0_TXD2 16 +#define PAD_GMAC0_TXD3 17 +#define PAD_GMAC0_TXEN 18 +#define PAD_GMAC0_TXC 19 + #define GPOUT_LOW 0 #define GPOUT_HIGH 1