diff mbox series

[2/5] drivers: mmc: sdhci-cadence: enable MMC_SDHCI_IO_ACCESSORS

Message ID 20221219142418.27949-3-pmalgujar@marvell.com
State New
Headers
Series drivers: mmc: sdhci-cadence: SD6 controller support |

Commit Message

Piyush Malgujar Dec. 19, 2022, 2:24 p.m. UTC 
  From: Jayanthi Annadurai <jannadurai@marvell.com>

Add support for CONFIG_MMC_SDHCI_IO_ACCESSORS for controller
specific register read and write APIs.

Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
---
 drivers/mmc/host/Kconfig         | 12 ++++++
 drivers/mmc/host/sdhci-cadence.c | 63 ++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+)

Comments

kernel test robot Jan. 1, 2023, 1:30 a.m. UTC | #1 
Hi Piyush,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v6.2-rc1 next-20221226]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Piyush-Malgujar/drivers-mmc-sdhci-cadence-SD6-controller-support/20221219-222703
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20221219142418.27949-3-pmalgujar%40marvell.com
patch subject: [PATCH 2/5] drivers: mmc: sdhci-cadence: enable MMC_SDHCI_IO_ACCESSORS
config: ia64-randconfig-c004-20230101
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/b087f4c6ad3997c952f7cfa57fb1fc5c4d1816ec
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Piyush-Malgujar/drivers-mmc-sdhci-cadence-SD6-controller-support/20221219-222703
        git checkout b087f4c6ad3997c952f7cfa57fb1fc5c4d1816ec
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o: in function `sdhci_cdns_probe':
>> drivers/mmc/host/sdhci-cadence.c:1730: undefined reference to `sdhci_pltfm_init'
   ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o: in function `sdhci_get_of_property':
>> drivers/mmc/host/sdhci-pltfm.h:94: undefined reference to `sdhci_get_property'
   ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o: in function `sdhci_cdns_probe':
>> drivers/mmc/host/sdhci-cadence.c:1765: undefined reference to `sdhci_enable_v4_mode'
>> ia64-linux-ld: drivers/mmc/host/sdhci-cadence.c:1767: undefined reference to `__sdhci_read_caps'
>> ia64-linux-ld: drivers/mmc/host/sdhci-cadence.c:1767: undefined reference to `sdhci_add_host'
>> ia64-linux-ld: drivers/mmc/host/sdhci-cadence.c:1773: undefined reference to `sdhci_pltfm_free'
   ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o: in function `sdhci_cdns_sd6_set_clock':
>> drivers/mmc/host/sdhci-cadence.c:1375: undefined reference to `sdhci_set_clock'
   ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o: in function `sdhci_cdns_set_uhs_signaling':
>> drivers/mmc/host/sdhci-cadence.c:1245: undefined reference to `sdhci_set_uhs_signaling'
   ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o:(.data.rel+0x8): undefined reference to `sdhci_pltfm_unregister'
>> ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o:(.data.rel.ro+0x80): undefined reference to `sdhci_set_bus_width'
>> ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o:(.data.rel.ro+0x98): undefined reference to `sdhci_reset'
>> ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o:(.data.rel.ro+0x120): undefined reference to `sdhci_set_clock'
   ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o:(.data.rel.ro+0x170): undefined reference to `sdhci_set_bus_width'
   ia64-linux-ld: drivers/mmc/host/sdhci-cadence.o:(.data.rel.ro+0x188): undefined reference to `sdhci_reset'

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for MMC_SDHCI_IO_ACCESSORS
   Depends on [n]: MMC [=y] && MMC_SDHCI [=n]
   Selected by [y]:
   - MMC_SDHCI_CN10K [=y] && MMC [=y]
   WARNING: unmet direct dependencies detected for MMC_SDHCI_CADENCE
   Depends on [n]: MMC [=y] && MMC_SDHCI_PLTFM [=n] && OF [=y]
   Selected by [y]:
   - MMC_SDHCI_CN10K [=y] && MMC [=y]


vim +1730 drivers/mmc/host/sdhci-cadence.c

d12990f9900f49 Piotr Sroka       2017-03-06  1705  
ff6af28faff53a Masahiro Yamada   2016-12-08  1706  static int sdhci_cdns_probe(struct platform_device *pdev)
ff6af28faff53a Masahiro Yamada   2016-12-08  1707  {
ff6af28faff53a Masahiro Yamada   2016-12-08  1708  	struct sdhci_host *host;
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1709  	const struct sdhci_cdns_of_data *data;
ff6af28faff53a Masahiro Yamada   2016-12-08  1710  	struct sdhci_pltfm_host *pltfm_host;
ff6af28faff53a Masahiro Yamada   2016-12-08  1711  	struct sdhci_cdns_priv *priv;
ff6af28faff53a Masahiro Yamada   2016-12-08  1712  	struct clk *clk;
ff6af28faff53a Masahiro Yamada   2016-12-08  1713  	int ret;
a89c472d8b55c5 Piotr Sroka       2017-03-21  1714  	struct device *dev = &pdev->dev;
ff6af28faff53a Masahiro Yamada   2016-12-08  1715  
edf98579065950 Piotr Sroka       2017-03-21  1716  	clk = devm_clk_get(dev, NULL);
ff6af28faff53a Masahiro Yamada   2016-12-08  1717  	if (IS_ERR(clk))
ff6af28faff53a Masahiro Yamada   2016-12-08  1718  		return PTR_ERR(clk);
ff6af28faff53a Masahiro Yamada   2016-12-08  1719  
ff6af28faff53a Masahiro Yamada   2016-12-08  1720  	ret = clk_prepare_enable(clk);
ff6af28faff53a Masahiro Yamada   2016-12-08  1721  	if (ret)
ff6af28faff53a Masahiro Yamada   2016-12-08  1722  		return ret;
ff6af28faff53a Masahiro Yamada   2016-12-08  1723  
18b587b45c13bb Masahiro Yamada   2020-03-12  1724  	data = of_device_get_match_data(dev);
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1725  	if (!data) {
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1726  		return PTR_ERR(clk);
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1727  		goto disable_clk;
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1728  	}
18b587b45c13bb Masahiro Yamada   2020-03-12  1729  
8bcfc23a884699 Dhananjay Kangude 2022-12-19 @1730  	host = sdhci_pltfm_init(pdev, data->pltfm_data, sizeof(*priv));
ff6af28faff53a Masahiro Yamada   2016-12-08  1731  	if (IS_ERR(host)) {
ff6af28faff53a Masahiro Yamada   2016-12-08  1732  		ret = PTR_ERR(host);
ff6af28faff53a Masahiro Yamada   2016-12-08  1733  		goto disable_clk;
ff6af28faff53a Masahiro Yamada   2016-12-08  1734  	}
ff6af28faff53a Masahiro Yamada   2016-12-08  1735  
ff6af28faff53a Masahiro Yamada   2016-12-08  1736  	pltfm_host = sdhci_priv(host);
ff6af28faff53a Masahiro Yamada   2016-12-08  1737  	pltfm_host->clk = clk;
ff6af28faff53a Masahiro Yamada   2016-12-08  1738  
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1739  	host->clk_mul = 0;
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1740  	host->max_clk = SDMCLK_MAX_FREQ;
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1741  	host->quirks |=  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1742  	host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
a232a8f2d10750 Masahiro Yamada   2017-08-23  1743  	priv = sdhci_pltfm_priv(pltfm_host);
ff6af28faff53a Masahiro Yamada   2016-12-08  1744  	priv->hrs_addr = host->ioaddr;
d12990f9900f49 Piotr Sroka       2017-03-06  1745  	priv->enhanced_strobe = false;
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1746  	priv->cdns_data = data->cdns_data;
ff6af28faff53a Masahiro Yamada   2016-12-08  1747  	host->ioaddr += SDHCI_CDNS_SRS_BASE;
d12990f9900f49 Piotr Sroka       2017-03-06  1748  	host->mmc_host_ops.hs400_enhanced_strobe =
d12990f9900f49 Piotr Sroka       2017-03-06  1749  				sdhci_cdns_hs400_enhanced_strobe;
ff6af28faff53a Masahiro Yamada   2016-12-08  1750  
861183f115cd80 Piotr Sroka       2017-04-11  1751  	sdhci_get_of_property(pdev);
861183f115cd80 Piotr Sroka       2017-04-11  1752  
ff6af28faff53a Masahiro Yamada   2016-12-08  1753  	ret = mmc_of_parse(host->mmc);
ff6af28faff53a Masahiro Yamada   2016-12-08  1754  	if (ret)
ff6af28faff53a Masahiro Yamada   2016-12-08  1755  		goto free;
ff6af28faff53a Masahiro Yamada   2016-12-08  1756  
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1757  	ret = data->phy_probe(pdev, priv);
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1758  	if (ret)
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1759  		goto free;
a232a8f2d10750 Masahiro Yamada   2017-08-23  1760  
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1761  	ret = priv->cdns_data->phy_init(priv);
a89c472d8b55c5 Piotr Sroka       2017-03-21  1762  	if (ret)
a89c472d8b55c5 Piotr Sroka       2017-03-21  1763  		goto free;
ff6af28faff53a Masahiro Yamada   2016-12-08  1764  
8bcfc23a884699 Dhananjay Kangude 2022-12-19 @1765  	sdhci_enable_v4_mode(host);
8bcfc23a884699 Dhananjay Kangude 2022-12-19  1766  	__sdhci_read_caps(host, NULL, NULL, NULL);
ff6af28faff53a Masahiro Yamada   2016-12-08 @1767  	ret = sdhci_add_host(host);
ff6af28faff53a Masahiro Yamada   2016-12-08  1768  	if (ret)
ff6af28faff53a Masahiro Yamada   2016-12-08  1769  		goto free;
ff6af28faff53a Masahiro Yamada   2016-12-08  1770  
ff6af28faff53a Masahiro Yamada   2016-12-08  1771  	return 0;
ff6af28faff53a Masahiro Yamada   2016-12-08  1772  free:
ff6af28faff53a Masahiro Yamada   2016-12-08 @1773  	sdhci_pltfm_free(pdev);
ff6af28faff53a Masahiro Yamada   2016-12-08  1774  disable_clk:
ff6af28faff53a Masahiro Yamada   2016-12-08  1775  	clk_disable_unprepare(clk);
ff6af28faff53a Masahiro Yamada   2016-12-08  1776  
ff6af28faff53a Masahiro Yamada   2016-12-08  1777  	return ret;
ff6af28faff53a Masahiro Yamada   2016-12-08  1778  }
ff6af28faff53a Masahiro Yamada   2016-12-08  1779
Adrian Hunter Jan. 11, 2023, 8:23 a.m. UTC | #2 
On 19/12/22 16:24, Piyush Malgujar wrote:
> From: Jayanthi Annadurai <jannadurai@marvell.com>
> 
> Add support for CONFIG_MMC_SDHCI_IO_ACCESSORS for controller
> specific register read and write APIs.
> 
> Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> ---
>  drivers/mmc/host/Kconfig         | 12 ++++++
>  drivers/mmc/host/sdhci-cadence.c | 63 ++++++++++++++++++++++++++++++++
>  2 files changed, 75 insertions(+)
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 5e19a961c34d7b5664ab2fd43cfba82dc90913ac..b5b2ae0bb4625bdb9d17acdbb1887c9caa3a1f32 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -262,6 +262,18 @@ config MMC_SDHCI_CADENCE
>  
>  	  If unsure, say N.
>  
> +config MMC_SDHCI_CN10K
> +	tristate "SDHCI Cadence support for Marvell CN10K platforms"
> +	select MMC_SDHCI_CADENCE
> +	select MMC_SDHCI_IO_ACCESSORS

Probably better to just add MMC_SDHCI_IO_ACCESSORS to 
config MMC_SDHCI_CADENCE and drop MMC_SDHCI_CN10K

> +	help
> +	  This selects the SDHCI cadence driver and IO Accessors
> +	  for Marvell CN10K platforms
> +
> +	  If you have Marvell CN10K platform, say Y or M here.
> +
> +	  If unsure, say N.
> +
>  config MMC_SDHCI_CNS3XXX
>  	tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
>  	depends on ARCH_CNS3XXX || COMPILE_TEST
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index 5332d19e489be936d6814feba4f0fc046f5e130e..6bf703f15bc5be7e3be4cb1144b78ec3585ec540 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -449,6 +449,61 @@ static u32 read_dqs_cmd_delay, clk_wrdqs_delay, clk_wr_delay, read_dqs_delay;
>  
>  static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host, unsigned int timing);
>  
> +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
> +static u32 sdhci_cdns_sd6_readl(struct sdhci_host *host, int reg)
> +{
> +	return readl(host->ioaddr + reg);
> +}
> +
> +static void sdhci_cdns_sd6_writel(struct sdhci_host *host, u32 val, int reg)
> +{
> +	writel(val, host->ioaddr + reg);
> +}
> +
> +static u16 sdhci_cdns_sd6_readw(struct sdhci_host *host, int reg)
> +{
> +	u32 val, regoff;
> +
> +	regoff = reg & ~3;
> +
> +	val = readl(host->ioaddr + regoff);
> +	if ((reg & 0x3) == 0)
> +		return (val & 0xFFFF);
> +	else
> +		return ((val >> 16) & 0xFFFF);
> +}
> +
> +static void sdhci_cdns_sd6_writew(struct sdhci_host *host, u16 val, int reg)
> +{
> +	writew(val, host->ioaddr + reg);
> +}
> +
> +static u8 sdhci_cdns_sd6_readb(struct sdhci_host *host, int reg)
> +{
> +	u32 val, regoff;
> +
> +	regoff = reg & ~3;
> +
> +	val = readl(host->ioaddr + regoff);
> +	switch (reg & 3) {
> +	case 0:
> +		return (val & 0xFF);
> +	case 1:
> +		return ((val >> 8) & 0xFF);
> +	case 2:
> +		return ((val >> 16) & 0xFF);
> +	case 3:
> +		return ((val >> 24) & 0xFF);
> +	}
> +	return 0;
> +}
> +
> +static void sdhci_cdns_sd6_writeb(struct sdhci_host *host, u8 val, int reg)
> +{
> +	writeb(val, host->ioaddr + reg);
> +}
> +#endif
> +
>  static int sdhci_cdns_sd6_phy_lock_dll(struct sdhci_cdns_sd6_phy *phy)
>  {
>  	u32 delay_element = phy->d.delay_element_org;
> @@ -1576,6 +1631,14 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
>  };
>  
>  static const struct sdhci_ops sdhci_cdns_sd6_ops = {
> +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
> +	.read_l = sdhci_cdns_sd6_readl,
> +	.write_l = sdhci_cdns_sd6_writel,
> +	.read_w = sdhci_cdns_sd6_readw,
> +	.write_w = sdhci_cdns_sd6_writew,
> +	.read_b = sdhci_cdns_sd6_readb,
> +	.write_b = sdhci_cdns_sd6_writeb,
> +#endif
>  	.get_max_clock = sdhci_cdns_get_max_clock,
>  	.set_clock = sdhci_cdns_sd6_set_clock,
>  	.get_timeout_clock = sdhci_cdns_get_timeout_clock,
Piyush Malgujar Jan. 12, 2023, 2:12 p.m. UTC | #3 
Hi Adrian, 

Thank you for the review comments.

On Wed, Jan 11, 2023 at 10:23:43AM +0200, Adrian Hunter wrote:
> On 19/12/22 16:24, Piyush Malgujar wrote:
> > From: Jayanthi Annadurai <jannadurai@marvell.com>
> > 
> > Add support for CONFIG_MMC_SDHCI_IO_ACCESSORS for controller
> > specific register read and write APIs.
> > 
> > Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
> > Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
> > ---
> >  drivers/mmc/host/Kconfig         | 12 ++++++
> >  drivers/mmc/host/sdhci-cadence.c | 63 ++++++++++++++++++++++++++++++++
> >  2 files changed, 75 insertions(+)
> > 
> > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> > index 5e19a961c34d7b5664ab2fd43cfba82dc90913ac..b5b2ae0bb4625bdb9d17acdbb1887c9caa3a1f32 100644
> > --- a/drivers/mmc/host/Kconfig
> > +++ b/drivers/mmc/host/Kconfig
> > @@ -262,6 +262,18 @@ config MMC_SDHCI_CADENCE
> >  
> >  	  If unsure, say N.
> >  
> > +config MMC_SDHCI_CN10K
> > +	tristate "SDHCI Cadence support for Marvell CN10K platforms"
> > +	select MMC_SDHCI_CADENCE
> > +	select MMC_SDHCI_IO_ACCESSORS
> 
> Probably better to just add MMC_SDHCI_IO_ACCESSORS to 
> config MMC_SDHCI_CADENCE and drop MMC_SDHCI_CN10K
> 

This reason behind this was to not force SDHCI_IO_ACCESSORS upon cadence users as some may not
require it owing to how cadence ip is integrated to soc.

> > +	help
> > +	  This selects the SDHCI cadence driver and IO Accessors
> > +	  for Marvell CN10K platforms
> > +
> > +	  If you have Marvell CN10K platform, say Y or M here.
> > +
> > +	  If unsure, say N.
> > +
> >  config MMC_SDHCI_CNS3XXX
> >  	tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
> >  	depends on ARCH_CNS3XXX || COMPILE_TEST
> > diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> > index 5332d19e489be936d6814feba4f0fc046f5e130e..6bf703f15bc5be7e3be4cb1144b78ec3585ec540 100644
> > --- a/drivers/mmc/host/sdhci-cadence.c
> > +++ b/drivers/mmc/host/sdhci-cadence.c
> > @@ -449,6 +449,61 @@ static u32 read_dqs_cmd_delay, clk_wrdqs_delay, clk_wr_delay, read_dqs_delay;
> >  
> >  static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host, unsigned int timing);
> >  
> > +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
> > +static u32 sdhci_cdns_sd6_readl(struct sdhci_host *host, int reg)
> > +{
> > +	return readl(host->ioaddr + reg);
> > +}
> > +
> > +static void sdhci_cdns_sd6_writel(struct sdhci_host *host, u32 val, int reg)
> > +{
> > +	writel(val, host->ioaddr + reg);
> > +}
> > +
> > +static u16 sdhci_cdns_sd6_readw(struct sdhci_host *host, int reg)
> > +{
> > +	u32 val, regoff;
> > +
> > +	regoff = reg & ~3;
> > +
> > +	val = readl(host->ioaddr + regoff);
> > +	if ((reg & 0x3) == 0)
> > +		return (val & 0xFFFF);
> > +	else
> > +		return ((val >> 16) & 0xFFFF);
> > +}
> > +
> > +static void sdhci_cdns_sd6_writew(struct sdhci_host *host, u16 val, int reg)
> > +{
> > +	writew(val, host->ioaddr + reg);
> > +}
> > +
> > +static u8 sdhci_cdns_sd6_readb(struct sdhci_host *host, int reg)
> > +{
> > +	u32 val, regoff;
> > +
> > +	regoff = reg & ~3;
> > +
> > +	val = readl(host->ioaddr + regoff);
> > +	switch (reg & 3) {
> > +	case 0:
> > +		return (val & 0xFF);
> > +	case 1:
> > +		return ((val >> 8) & 0xFF);
> > +	case 2:
> > +		return ((val >> 16) & 0xFF);
> > +	case 3:
> > +		return ((val >> 24) & 0xFF);
> > +	}
> > +	return 0;
> > +}
> > +
> > +static void sdhci_cdns_sd6_writeb(struct sdhci_host *host, u8 val, int reg)
> > +{
> > +	writeb(val, host->ioaddr + reg);
> > +}
> > +#endif
> > +
> >  static int sdhci_cdns_sd6_phy_lock_dll(struct sdhci_cdns_sd6_phy *phy)
> >  {
> >  	u32 delay_element = phy->d.delay_element_org;
> > @@ -1576,6 +1631,14 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
> >  };
> >  
> >  static const struct sdhci_ops sdhci_cdns_sd6_ops = {
> > +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
> > +	.read_l = sdhci_cdns_sd6_readl,
> > +	.write_l = sdhci_cdns_sd6_writel,
> > +	.read_w = sdhci_cdns_sd6_readw,
> > +	.write_w = sdhci_cdns_sd6_writew,
> > +	.read_b = sdhci_cdns_sd6_readb,
> > +	.write_b = sdhci_cdns_sd6_writeb,
> > +#endif
> >  	.get_max_clock = sdhci_cdns_get_max_clock,
> >  	.set_clock = sdhci_cdns_sd6_set_clock,
> >  	.get_timeout_clock = sdhci_cdns_get_timeout_clock,
> 

Rest of the comments will be taken care in v2.

Thanks,
Piyush
Adrian Hunter Jan. 13, 2023, 7:20 a.m. UTC | #4 
On 12/01/23 16:12, Piyush Malgujar wrote:
> Hi Adrian, 
> 
> Thank you for the review comments.
> 
> On Wed, Jan 11, 2023 at 10:23:43AM +0200, Adrian Hunter wrote:
>> On 19/12/22 16:24, Piyush Malgujar wrote:
>>> From: Jayanthi Annadurai <jannadurai@marvell.com>
>>>
>>> Add support for CONFIG_MMC_SDHCI_IO_ACCESSORS for controller
>>> specific register read and write APIs.
>>>
>>> Signed-off-by: Jayanthi Annadurai <jannadurai@marvell.com>
>>> Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
>>> ---
>>>  drivers/mmc/host/Kconfig         | 12 ++++++
>>>  drivers/mmc/host/sdhci-cadence.c | 63 ++++++++++++++++++++++++++++++++
>>>  2 files changed, 75 insertions(+)
>>>
>>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>>> index 5e19a961c34d7b5664ab2fd43cfba82dc90913ac..b5b2ae0bb4625bdb9d17acdbb1887c9caa3a1f32 100644
>>> --- a/drivers/mmc/host/Kconfig
>>> +++ b/drivers/mmc/host/Kconfig
>>> @@ -262,6 +262,18 @@ config MMC_SDHCI_CADENCE
>>>  
>>>  	  If unsure, say N.
>>>  
>>> +config MMC_SDHCI_CN10K
>>> +	tristate "SDHCI Cadence support for Marvell CN10K platforms"
>>> +	select MMC_SDHCI_CADENCE
>>> +	select MMC_SDHCI_IO_ACCESSORS
>>
>> Probably better to just add MMC_SDHCI_IO_ACCESSORS to 
>> config MMC_SDHCI_CADENCE and drop MMC_SDHCI_CN10K
>>
> 
> This reason behind this was to not force SDHCI_IO_ACCESSORS upon cadence users as some may not
> require it owing to how cadence ip is integrated to soc.

In practice, it makes no difference to performance and adds a
negligible amount of code, so it is not worth the extra complexity
to make it conditional.

> 
>>> +	help
>>> +	  This selects the SDHCI cadence driver and IO Accessors
>>> +	  for Marvell CN10K platforms
>>> +
>>> +	  If you have Marvell CN10K platform, say Y or M here.
>>> +
>>> +	  If unsure, say N.
>>> +
>>>  config MMC_SDHCI_CNS3XXX
>>>  	tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
>>>  	depends on ARCH_CNS3XXX || COMPILE_TEST
>>> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
>>> index 5332d19e489be936d6814feba4f0fc046f5e130e..6bf703f15bc5be7e3be4cb1144b78ec3585ec540 100644
>>> --- a/drivers/mmc/host/sdhci-cadence.c
>>> +++ b/drivers/mmc/host/sdhci-cadence.c
>>> @@ -449,6 +449,61 @@ static u32 read_dqs_cmd_delay, clk_wrdqs_delay, clk_wr_delay, read_dqs_delay;
>>>  
>>>  static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host, unsigned int timing);
>>>  
>>> +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
>>> +static u32 sdhci_cdns_sd6_readl(struct sdhci_host *host, int reg)
>>> +{
>>> +	return readl(host->ioaddr + reg);
>>> +}
>>> +
>>> +static void sdhci_cdns_sd6_writel(struct sdhci_host *host, u32 val, int reg)
>>> +{
>>> +	writel(val, host->ioaddr + reg);
>>> +}
>>> +
>>> +static u16 sdhci_cdns_sd6_readw(struct sdhci_host *host, int reg)
>>> +{
>>> +	u32 val, regoff;
>>> +
>>> +	regoff = reg & ~3;
>>> +
>>> +	val = readl(host->ioaddr + regoff);
>>> +	if ((reg & 0x3) == 0)
>>> +		return (val & 0xFFFF);
>>> +	else
>>> +		return ((val >> 16) & 0xFFFF);
>>> +}
>>> +
>>> +static void sdhci_cdns_sd6_writew(struct sdhci_host *host, u16 val, int reg)
>>> +{
>>> +	writew(val, host->ioaddr + reg);
>>> +}
>>> +
>>> +static u8 sdhci_cdns_sd6_readb(struct sdhci_host *host, int reg)
>>> +{
>>> +	u32 val, regoff;
>>> +
>>> +	regoff = reg & ~3;
>>> +
>>> +	val = readl(host->ioaddr + regoff);
>>> +	switch (reg & 3) {
>>> +	case 0:
>>> +		return (val & 0xFF);
>>> +	case 1:
>>> +		return ((val >> 8) & 0xFF);
>>> +	case 2:
>>> +		return ((val >> 16) & 0xFF);
>>> +	case 3:
>>> +		return ((val >> 24) & 0xFF);
>>> +	}
>>> +	return 0;
>>> +}
>>> +
>>> +static void sdhci_cdns_sd6_writeb(struct sdhci_host *host, u8 val, int reg)
>>> +{
>>> +	writeb(val, host->ioaddr + reg);
>>> +}
>>> +#endif
>>> +
>>>  static int sdhci_cdns_sd6_phy_lock_dll(struct sdhci_cdns_sd6_phy *phy)
>>>  {
>>>  	u32 delay_element = phy->d.delay_element_org;
>>> @@ -1576,6 +1631,14 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
>>>  };
>>>  
>>>  static const struct sdhci_ops sdhci_cdns_sd6_ops = {
>>> +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
>>> +	.read_l = sdhci_cdns_sd6_readl,
>>> +	.write_l = sdhci_cdns_sd6_writel,
>>> +	.read_w = sdhci_cdns_sd6_readw,
>>> +	.write_w = sdhci_cdns_sd6_writew,
>>> +	.read_b = sdhci_cdns_sd6_readb,
>>> +	.write_b = sdhci_cdns_sd6_writeb,
>>> +#endif
>>>  	.get_max_clock = sdhci_cdns_get_max_clock,
>>>  	.set_clock = sdhci_cdns_sd6_set_clock,
>>>  	.get_timeout_clock = sdhci_cdns_get_timeout_clock,
>>
> 
> Rest of the comments will be taken care in v2.
> 
> Thanks,
> Piyush
diff mbox series

Patch

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5e19a961c34d7b5664ab2fd43cfba82dc90913ac..b5b2ae0bb4625bdb9d17acdbb1887c9caa3a1f32 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -262,6 +262,18 @@  config MMC_SDHCI_CADENCE
 
 	  If unsure, say N.
 
+config MMC_SDHCI_CN10K
+	tristate "SDHCI Cadence support for Marvell CN10K platforms"
+	select MMC_SDHCI_CADENCE
+	select MMC_SDHCI_IO_ACCESSORS
+	help
+	  This selects the SDHCI cadence driver and IO Accessors
+	  for Marvell CN10K platforms
+
+	  If you have Marvell CN10K platform, say Y or M here.
+
+	  If unsure, say N.
+
 config MMC_SDHCI_CNS3XXX
 	tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
 	depends on ARCH_CNS3XXX || COMPILE_TEST
diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 5332d19e489be936d6814feba4f0fc046f5e130e..6bf703f15bc5be7e3be4cb1144b78ec3585ec540 100644
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -449,6 +449,61 @@  static u32 read_dqs_cmd_delay, clk_wrdqs_delay, clk_wr_delay, read_dqs_delay;
 
 static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host, unsigned int timing);
 
+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+static u32 sdhci_cdns_sd6_readl(struct sdhci_host *host, int reg)
+{
+	return readl(host->ioaddr + reg);
+}
+
+static void sdhci_cdns_sd6_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	writel(val, host->ioaddr + reg);
+}
+
+static u16 sdhci_cdns_sd6_readw(struct sdhci_host *host, int reg)
+{
+	u32 val, regoff;
+
+	regoff = reg & ~3;
+
+	val = readl(host->ioaddr + regoff);
+	if ((reg & 0x3) == 0)
+		return (val & 0xFFFF);
+	else
+		return ((val >> 16) & 0xFFFF);
+}
+
+static void sdhci_cdns_sd6_writew(struct sdhci_host *host, u16 val, int reg)
+{
+	writew(val, host->ioaddr + reg);
+}
+
+static u8 sdhci_cdns_sd6_readb(struct sdhci_host *host, int reg)
+{
+	u32 val, regoff;
+
+	regoff = reg & ~3;
+
+	val = readl(host->ioaddr + regoff);
+	switch (reg & 3) {
+	case 0:
+		return (val & 0xFF);
+	case 1:
+		return ((val >> 8) & 0xFF);
+	case 2:
+		return ((val >> 16) & 0xFF);
+	case 3:
+		return ((val >> 24) & 0xFF);
+	}
+	return 0;
+}
+
+static void sdhci_cdns_sd6_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+	writeb(val, host->ioaddr + reg);
+}
+#endif
+
 static int sdhci_cdns_sd6_phy_lock_dll(struct sdhci_cdns_sd6_phy *phy)
 {
 	u32 delay_element = phy->d.delay_element_org;
@@ -1576,6 +1631,14 @@  static const struct sdhci_ops sdhci_cdns_sd4_ops = {
 };
 
 static const struct sdhci_ops sdhci_cdns_sd6_ops = {
+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+	.read_l = sdhci_cdns_sd6_readl,
+	.write_l = sdhci_cdns_sd6_writel,
+	.read_w = sdhci_cdns_sd6_readw,
+	.write_w = sdhci_cdns_sd6_writew,
+	.read_b = sdhci_cdns_sd6_readb,
+	.write_b = sdhci_cdns_sd6_writeb,
+#endif
 	.get_max_clock = sdhci_cdns_get_max_clock,
 	.set_clock = sdhci_cdns_sd6_set_clock,
 	.get_timeout_clock = sdhci_cdns_get_timeout_clock,