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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m20-20020aa7c2d4000000b00461f0d84ee1si2476697edp.228.2022.12.16.10.42.28; Fri, 16 Dec 2022 10:42:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@hpe.com header.s=pps0720 header.b="C2si/ZN3"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=hpe.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231345AbiLPShw (ORCPT + 99 others); Fri, 16 Dec 2022 13:37:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231759AbiLPShd (ORCPT ); Fri, 16 Dec 2022 13:37:33 -0500 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77A0A2B243; Fri, 16 Dec 2022 10:37:31 -0800 (PST) Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BGFLFeN032457; Fri, 16 Dec 2022 18:37:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : subject : date : message-id : in-reply-to : references; s=pps0720; bh=6j+P5rPMSR/V07V6V4yi3Apu55sbMKl2KWyLgzQ4qoo=; b=C2si/ZN3/56eOcCuRdXfkhx8BbteGYb3jon1qu5L5rFAIInI08sYqkoKZpZv37atQKXr kP6+1CFlWYBBKGshCOg/zcFQi/ca755rSB5XCQ1g9z4qUMLoaL/ZpH6ykcKy6HNjIY4P zoRWM1FPdwg7Y/aW6bQYvovpZJx+hbf68tmPa8hhusmTm89Q1BdStmy27ncndCvTXQ+Y bBnTALazpNaqg/jr3hAbEUPwsG9W4hrylgyA1B/wtSa9moLkOZ6W4bYdjnHM5sFJpMxF 7i2q+BKoHbM3HqwOApeN6Bt3RbvPlz6UzatwJDyfcetaFOkIzyUAUlx/IOMYx9hlUbL7 eg== Received: from p1lg14879.it.hpe.com (p1lg14879.it.hpe.com [16.230.97.200]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3mgu8898yq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Dec 2022 18:37:06 +0000 Received: from p1lg14885.dc01.its.hpecorp.net (unknown [10.119.18.236]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by p1lg14879.it.hpe.com (Postfix) with ESMTPS id 0AB2C31096; Fri, 16 Dec 2022 18:37:06 +0000 (UTC) Received: from hpe.com (unknown [16.231.227.36]) by p1lg14885.dc01.its.hpecorp.net (Postfix) with ESMTP id 75B4D8048F9; Fri, 16 Dec 2022 18:37:05 +0000 (UTC) From: nick.hawkins@hpe.com To: verdun@hpe.com, nick.hawkins@hpe.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, linux@armlinux.org.uk, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 1/6] i2c: hpe: Add GXP SoC I2C Controller Date: Fri, 16 Dec 2022 12:35:27 -0600 Message-Id: <20221216183532.78933-2-nick.hawkins@hpe.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221216183532.78933-1-nick.hawkins@hpe.com> References: <20221216183532.78933-1-nick.hawkins@hpe.com> X-Proofpoint-GUID: Qox2BWv_eBdfLo0M1YlV6jWMOxjcHCru X-Proofpoint-ORIG-GUID: Qox2BWv_eBdfLo0M1YlV6jWMOxjcHCru X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-16_12,2022-12-15_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 clxscore=1015 suspectscore=0 bulkscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212160162 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752397168381444773?= X-GMAIL-MSGID: =?utf-8?q?1752397168381444773?= From: Nick Hawkins The GXP SoC supports 10 I2C engines. Each I2C engine is completely independent and can function both as an I2C master and I2C slave. The I2C master can operate in a multi master environment. The engines support a scalable speed from 8kHZ to 1.5 Mhz. Signed-off-by: Nick Hawkins --- drivers/i2c/busses/Kconfig | 7 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-gxp.c | 641 +++++++++++++++++++++++++++++++++++ 3 files changed, 649 insertions(+) create mode 100644 drivers/i2c/busses/i2c-gxp.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index e50f9603d189..8b3951e0ca5c 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -1457,4 +1457,11 @@ config I2C_VIRTIO This driver can also be built as a module. If so, the module will be called i2c-virtio. +config I2C_GXP + tristate "GXP I2C Interface" + depends on ARCH_HPE_GXP || COMPILE_TEST + help + This enables support for GXP I2C interface. The I2C engines can be + either I2C master or I2C slaves. + endmenu diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index e73cdb1d2b5a..dcc96eab6d68 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -127,6 +127,7 @@ obj-$(CONFIG_I2C_THUNDERX) += i2c-thunderx.o obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o +obj-$(CONFIG_I2C_GXP) += i2c-gxp.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o diff --git a/drivers/i2c/busses/i2c-gxp.c b/drivers/i2c/busses/i2c-gxp.c new file mode 100644 index 000000000000..a67c0c4d7520 --- /dev/null +++ b/drivers/i2c/busses/i2c-gxp.c @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */ + +#include +#include +#include +#include +#include +#include +#include + +#define GXP_MAX_I2C_ENGINE 10 +static const char * const gxp_i2c_name[] = { + "gxp-i2c0", "gxp-i2c1", "gxp-i2c2", "gxp-i2c3", + "gxp-i2c4", "gxp-i2c5", "gxp-i2c6", "gxp-i2c7", + "gxp-i2c8", "gxp-i2c9" }; + +/* Default value */ +#define GXP_I2C_BIT_RATE 100000 /* 100kHz */ + +/* GXP I2C Global interrupt status/enable register*/ +#define GXP_I2CINTSTAT 0x00 +#define GXP_I2CINTEN 0x04 + +/* GXP I2C registers */ +#define GXP_I2CSTAT 0x00 +#define MASK_STOP_EVENT 0x20 +#define MASK_ACK 0x08 +#define MASK_RW 0x04 +#define GXP_I2CEVTERR 0x01 +#define MASK_SLAVE_CMD_EVENT 0x01 +#define MASK_SLAVE_DATA_EVENT 0x02 +#define MASK_MASTER_EVENT 0x10 +#define GXP_I2CSNPDAT 0x02 +#define GXP_I2CMCMD 0x04 +#define GXP_I2CSCMD 0x06 +#define GXP_I2CSNPAA 0x09 +#define GXP_I2CADVFEAT 0x0A +#define GXP_I2COWNADR 0x0B +#define GXP_I2CFREQDIV 0x0C +#define GXP_I2CFLTFAIR 0x0D +#define GXP_I2CTMOEDG 0x0E +#define GXP_I2CCYCTIM 0x0F + +static bool i2c_global_init_done; + +enum { + GXP_I2C_IDLE = 0, + GXP_I2C_ADDR_PHASE, + GXP_I2C_RDATA_PHASE, + GXP_I2C_WDATA_PHASE, + GXP_I2C_ADDR_NACK, + GXP_I2C_DATA_NACK, + GXP_I2C_ERROR, + GXP_I2C_COMP +}; + +struct gxp_i2c_drvdata { + struct device *dev; + void __iomem *base; + u32 bus_frequency; + int engine; + int irq; + struct completion completion; + struct i2c_adapter adapter; + struct i2c_msg *curr_msg; + int msgs_remaining; + int msgs_num; + u8 *buf; + size_t buf_remaining; + unsigned char state; + struct i2c_client *slave; + unsigned char stopped; +}; + +static struct regmap *i2cg_map; + +static void gxp_i2c_start(struct gxp_i2c_drvdata *drvdata) +{ + void __iomem *base = drvdata->base; + u16 value; + + drvdata->buf = drvdata->curr_msg->buf; + drvdata->buf_remaining = drvdata->curr_msg->len; + + /* Note: Address in struct i2c_msg is 7 bits */ + value = drvdata->curr_msg->addr << 9; + + if (drvdata->curr_msg->flags & I2C_M_RD) { + /* Read */ + value |= 0x05; + } else { + /* Write */ + value |= 0x01; + } + + drvdata->state = GXP_I2C_ADDR_PHASE; + writew(value, base + GXP_I2CMCMD); +} + +static int gxp_i2c_master_xfer(struct i2c_adapter *adapter, + struct i2c_msg *msgs, int num) +{ + int ret; + struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(adapter); + unsigned long time_left; + + drvdata->msgs_remaining = num; + drvdata->curr_msg = msgs; + drvdata->msgs_num = num; + reinit_completion(&drvdata->completion); + + gxp_i2c_start(drvdata); + + time_left = wait_for_completion_timeout(&drvdata->completion, + adapter->timeout); + ret = num - drvdata->msgs_remaining; + if (time_left == 0) { + switch (drvdata->state) { + case GXP_I2C_WDATA_PHASE: + dev_err(drvdata->dev, + "gxp_i2c_start:write Data phase timeout at msg[%d]\n", + ret); + break; + case GXP_I2C_RDATA_PHASE: + dev_err(drvdata->dev, + "gxp_i2c_start:read Data phase timeout at msg[%d]\n", + ret); + break; + case GXP_I2C_ADDR_PHASE: + dev_err(drvdata->dev, + "gxp_i2c_start:Addr phase timeout\n"); + break; + default: + dev_err(drvdata->dev, + "gxp_i2c_start:i2c transfer timeout state=%d\n", + drvdata->state); + break; + } + return -ETIMEDOUT; + } + + if (drvdata->state == GXP_I2C_ADDR_NACK) { + dev_dbg(drvdata->dev, + "gxp_i2c_start:No ACK for address phase\n"); + return -EIO; + } else if (drvdata->state == GXP_I2C_DATA_NACK) { + dev_dbg(drvdata->dev, "gxp_i2c_start:No ACK for data phase\n"); + return -EIO; + } + + return ret; +} + +static u32 gxp_i2c_func(struct i2c_adapter *adap) +{ +#if IS_ENABLED(CONFIG_I2C_SLAVE) + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE; +#else + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +#endif +} + +#if IS_ENABLED(CONFIG_I2C_SLAVE) +static int gxp_i2c_reg_slave(struct i2c_client *slave) +{ + struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(slave->adapter); + void __iomem *base = drvdata->base; + + pr_info("[%s] I2C engine%d addr:0x%02x\n", __func__, drvdata->engine, slave->addr); + if (drvdata->slave) + return -EBUSY; + + if (slave->flags & I2C_CLIENT_TEN) + return -EAFNOSUPPORT; + + drvdata->slave = slave; + + writeb(slave->addr << 1, base + GXP_I2COWNADR); + writeb(0x69, base + GXP_I2CSCMD); + + return 0; +} + +static int gxp_i2c_unreg_slave(struct i2c_client *slave) +{ + struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(slave->adapter); + void __iomem *base = drvdata->base; + + pr_info("[%s] I2C engine%d\n", __func__, drvdata->engine); + WARN_ON(!drvdata->slave); + + writeb(0x00, base + GXP_I2COWNADR); + writeb(0xF0, base + GXP_I2CSCMD); + + drvdata->slave = NULL; + + return 0; +} +#endif + +static const struct i2c_algorithm gxp_i2c_algo = { + .master_xfer = gxp_i2c_master_xfer, + .functionality = gxp_i2c_func, +#if IS_ENABLED(CONFIG_I2C_SLAVE) + .reg_slave = gxp_i2c_reg_slave, + .unreg_slave = gxp_i2c_unreg_slave, +#endif +}; + +static void gxp_i2c_stop(struct gxp_i2c_drvdata *drvdata) +{ + void __iomem *base = drvdata->base; + + /* Clear event and send stop */ + writeb(0x82, base + GXP_I2CMCMD); + + complete(&drvdata->completion); +} + +static void gxp_i2c_restart(struct gxp_i2c_drvdata *drvdata) +{ + void __iomem *base = drvdata->base; + u16 value; + + drvdata->buf = drvdata->curr_msg->buf; + drvdata->buf_remaining = drvdata->curr_msg->len; + + value = drvdata->curr_msg->addr << 9; + + if (drvdata->curr_msg->flags & I2C_M_RD) { + /* Read and clear master event */ + value |= 0x85; + } else { + /* Write and clear master event */ + value |= 0x81; + } + + drvdata->state = GXP_I2C_ADDR_PHASE; + + writew(value, base + GXP_I2CMCMD); +} + +static void gxp_i2c_chk_addr_ack(struct gxp_i2c_drvdata *drvdata) +{ + void __iomem *base = drvdata->base; + u16 value; + + value = readb(base + GXP_I2CSTAT); + if (!(value & MASK_ACK)) { + /* Got no ack, stop */ + drvdata->state = GXP_I2C_ADDR_NACK; + gxp_i2c_stop(drvdata); + return; + } + + if (drvdata->curr_msg->flags & I2C_M_RD) { + /* Start to read data from slave */ + if (drvdata->buf_remaining == 0) { + /* No more data to read, stop */ + drvdata->msgs_remaining--; + drvdata->state = GXP_I2C_COMP; + gxp_i2c_stop(drvdata); + return; + } + drvdata->state = GXP_I2C_RDATA_PHASE; + + if (drvdata->buf_remaining == 1) { + /* The last data, do not ack */ + writeb(0x84, base + GXP_I2CMCMD); + } else { + /* Read data and ack it */ + writeb(0x8C, base + GXP_I2CMCMD); + } + } else { + /* Start to write first data to slave */ + if (drvdata->buf_remaining == 0) { + /* No more data to write, stop */ + drvdata->msgs_remaining--; + drvdata->state = GXP_I2C_COMP; + gxp_i2c_stop(drvdata); + return; + } + value = *drvdata->buf; + value = value << 8; + /* Clear master event */ + value |= 0x80; + drvdata->buf++; + drvdata->buf_remaining--; + drvdata->state = GXP_I2C_WDATA_PHASE; + writew(value, base + GXP_I2CMCMD); + } +} + +static void gxp_i2c_ack_data(struct gxp_i2c_drvdata *drvdata) +{ + void __iomem *base = drvdata->base; + u8 value; + + /* Store the data returned */ + value = readb(base + GXP_I2CSNPDAT); + *drvdata->buf = value; + drvdata->buf++; + drvdata->buf_remaining--; + + if (drvdata->buf_remaining == 0) { + /* No more data, this message is completed. */ + drvdata->msgs_remaining--; + + if (drvdata->msgs_remaining == 0) { + /* No more messages, stop */ + drvdata->state = GXP_I2C_COMP; + gxp_i2c_stop(drvdata); + return; + } + /* Move to next message and start transfer */ + drvdata->curr_msg++; + gxp_i2c_restart(drvdata); + return; + } + + /* Ack the slave to make it send next byte */ + drvdata->state = GXP_I2C_RDATA_PHASE; + if (drvdata->buf_remaining == 1) { + /* The last data, do not ack */ + writeb(0x84, base + GXP_I2CMCMD); + } else { + /* Read data and ack it */ + writeb(0x8C, base + GXP_I2CMCMD); + } +} + +static void gxp_i2c_chk_data_ack(struct gxp_i2c_drvdata *drvdata) +{ + void __iomem *base = drvdata->base; + u16 value; + + value = readb(base + GXP_I2CSTAT); + if (!(value & MASK_ACK)) { + /* Received No ack, stop */ + drvdata->state = GXP_I2C_DATA_NACK; + gxp_i2c_stop(drvdata); + return; + } + + /* Got ack, check if there is more data to write */ + if (drvdata->buf_remaining == 0) { + /* No more data, this message is completed */ + drvdata->msgs_remaining--; + + if (drvdata->msgs_remaining == 0) { + /* No more messages, stop */ + drvdata->state = GXP_I2C_COMP; + gxp_i2c_stop(drvdata); + return; + } + /* Move to next message and start transfer */ + drvdata->curr_msg++; + gxp_i2c_restart(drvdata); + return; + } + + /* Write data to slave */ + value = *drvdata->buf; + value = value << 8; + + /* Clear master event */ + value |= 0x80; + drvdata->buf++; + drvdata->buf_remaining--; + drvdata->state = GXP_I2C_WDATA_PHASE; + writew(value, base + GXP_I2CMCMD); +} + +#if IS_ENABLED(CONFIG_I2C_SLAVE) +static bool gxp_i2c_slave_irq_handler(struct gxp_i2c_drvdata *drvdata) +{ + void __iomem *base = drvdata->base; + u16 value; + u8 buf; + int ret; + + value = readb(base + GXP_I2CEVTERR); + + /* Received start or stop event */ + if (value & MASK_SLAVE_CMD_EVENT) { + value = readb(base + GXP_I2CSTAT); + /* Master sent stop */ + if (value & MASK_STOP_EVENT) { + if (drvdata->stopped == 0) + i2c_slave_event(drvdata->slave, I2C_SLAVE_STOP, &buf); + writeb(0x69, base + GXP_I2CSCMD); + drvdata->stopped = 1; + } else { + /* Master sent start and wants to read */ + drvdata->stopped = 0; + if (value & MASK_RW) { + i2c_slave_event(drvdata->slave, + I2C_SLAVE_READ_REQUESTED, &buf); + value = buf << 8 | 0x61; + writew(value, base + GXP_I2CSCMD); + } else { + /* Master wants to write to us */ + ret = i2c_slave_event(drvdata->slave, + I2C_SLAVE_WRITE_REQUESTED, &buf); + if (!ret) { + /* Ack next byte from master */ + writeb(0x69, base + GXP_I2CSCMD); + } else { + /* Nack next byte from master */ + writeb(0x61, base + GXP_I2CSCMD); + } + } + } + } else if (value & MASK_SLAVE_DATA_EVENT) { + value = readb(base + GXP_I2CSTAT); + /* Master wants to read */ + if (value & MASK_RW) { + /* Master wants another byte */ + if (value & MASK_ACK) { + i2c_slave_event(drvdata->slave, + I2C_SLAVE_READ_PROCESSED, &buf); + value = buf << 8 | 0x61; + writew(value, base + GXP_I2CSCMD); + } else { + /* No more bytes needed */ + writew(0x69, base + GXP_I2CSCMD); + } + } else { + /* Master wants to write to us */ + value = readb(base + GXP_I2CSNPDAT); + buf = (uint8_t)value; + ret = i2c_slave_event(drvdata->slave, + I2C_SLAVE_WRITE_RECEIVED, &buf); + if (!ret) { + /* Ack next byte from master */ + writeb(0x69, base + GXP_I2CSCMD); + } else { + /* Nack next byte from master */ + writeb(0x61, base + GXP_I2CSCMD); + } + } + } else { + return false; + } + + return true; +} +#endif + +static irqreturn_t gxp_i2c_irq_handler(int irq, void *_drvdata) +{ + struct gxp_i2c_drvdata *drvdata = (struct gxp_i2c_drvdata *)_drvdata; + u32 value; + void __iomem *base = drvdata->base; + + regmap_read(i2cg_map, GXP_I2CINTSTAT, &value); + if (!(value & (1 << drvdata->engine))) + return IRQ_NONE; + + value = readb(base + GXP_I2CEVTERR); + + /* Error */ + if (value & ~(MASK_MASTER_EVENT | MASK_SLAVE_CMD_EVENT | + MASK_SLAVE_DATA_EVENT)) { + pr_alert("[%s] I2C Error, GXP_I2CEVTERR = 0x%x\n", __func__, + value); + + /* Clear all events */ + writeb(0x00, base + GXP_I2CEVTERR); + drvdata->state = GXP_I2C_ERROR; + gxp_i2c_stop(drvdata); + return IRQ_HANDLED; + } + +#if IS_ENABLED(CONFIG_I2C_SLAVE) + /* Slave mode */ + if (value & (MASK_SLAVE_CMD_EVENT | MASK_SLAVE_DATA_EVENT)) { + if (gxp_i2c_slave_irq_handler(drvdata)) + return IRQ_HANDLED; + pr_alert("[%s] I2C Error, GXP_I2CEVTERR = 0x%x\n", + __func__, value); + return IRQ_NONE; + } +#endif + + /* Master mode */ + switch (drvdata->state) { + case GXP_I2C_ADDR_PHASE: + gxp_i2c_chk_addr_ack(drvdata); + break; + + case GXP_I2C_RDATA_PHASE: + gxp_i2c_ack_data(drvdata); + break; + + case GXP_I2C_WDATA_PHASE: + gxp_i2c_chk_data_ack(drvdata); + break; + } + + return IRQ_HANDLED; +} + +static void gxp_i2c_init(struct gxp_i2c_drvdata *drvdata) +{ + void __iomem *base = drvdata->base; + + drvdata->state = GXP_I2C_IDLE; + writeb(2000000 / drvdata->bus_frequency, base + GXP_I2CFREQDIV); + writeb(0x32, base + GXP_I2CFLTFAIR); + writeb(0x0a, base + GXP_I2CTMOEDG); + writeb(0x00, base + GXP_I2CCYCTIM); + writeb(0x00, base + GXP_I2CSNPAA); + writeb(0x00, base + GXP_I2CADVFEAT); + writeb(0xF0, base + GXP_I2CSCMD); + writeb(0x80, base + GXP_I2CMCMD); + writeb(0x00, base + GXP_I2CEVTERR); + writeb(0x00, base + GXP_I2COWNADR); +} + +static int gxp_i2c_probe(struct platform_device *pdev) +{ + struct gxp_i2c_drvdata *drvdata; + int rc; + struct resource *res; + struct i2c_adapter *adapter; + + if (!i2c_global_init_done) { + pr_info("[%s] I2c global init\n", __func__); + i2cg_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "hpe,sysreg-phandle"); + if (IS_ERR(i2cg_map)) { + dev_err(&pdev->dev, "failed to map i2cg_handle\n"); + return -ENODEV; + } + + /* Disable interrupt */ + regmap_update_bits(i2cg_map, GXP_I2CINTEN, 0x00000FFF, 0); + i2c_global_init_done = true; + } + + drvdata = devm_kzalloc(&pdev->dev, sizeof(struct gxp_i2c_drvdata), + GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + platform_set_drvdata(pdev, drvdata); + drvdata->dev = &pdev->dev; + init_completion(&drvdata->completion); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + drvdata->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(drvdata->base)) + return PTR_ERR(drvdata->base); + + drvdata->engine = (res->start & 0xf00) >> 8; + pr_info("%s: i2c engine%d\n", __func__, drvdata->engine); + if (drvdata->engine >= GXP_MAX_I2C_ENGINE) { + dev_err(&pdev->dev, "i2c engine% is unsupported\n", + drvdata->engine); + return -EINVAL; + } + + rc = platform_get_irq(pdev, 0); + if (rc < 0) { + dev_err(&pdev->dev, "unable to obtain IRQ number\n"); + return rc; + } + + drvdata->irq = rc; + pr_info("[%s] i2c engine%d, rq = %d\n", __func__, drvdata->engine, + drvdata->irq); + + rc = devm_request_irq(&pdev->dev, drvdata->irq, gxp_i2c_irq_handler, + IRQF_SHARED, gxp_i2c_name[drvdata->engine], drvdata); + if (rc < 0) { + dev_err(&pdev->dev, "irq request failed\n"); + return rc; + } + + rc = of_property_read_u32(pdev->dev.of_node, + "hpe,i2c-max-bus-freq", &drvdata->bus_frequency); + if (rc < 0) { + dev_info(&pdev->dev, + "Could not read bus-frequency property, use default frequency:100000\n"); + drvdata->bus_frequency = GXP_I2C_BIT_RATE; + } + + gxp_i2c_init(drvdata); + + /* Enable interrupt */ + regmap_update_bits(i2cg_map, GXP_I2CINTEN, BIT(drvdata->engine), + BIT(drvdata->engine)); + + adapter = &drvdata->adapter; + i2c_set_adapdata(adapter, drvdata); + + adapter->owner = THIS_MODULE; + adapter->class = I2C_CLASS_DEPRECATED; + strscpy(adapter->name, "HPE GXP I2C adapter", sizeof(adapter->name)); + adapter->algo = &gxp_i2c_algo; + adapter->dev.parent = &pdev->dev; + adapter->dev.of_node = pdev->dev.of_node; + + rc = i2c_add_adapter(adapter); + if (rc) + dev_err(&pdev->dev, "i2c add adapter failed\n"); + + return rc; +} + +static int gxp_i2c_remove(struct platform_device *pdev) +{ + struct gxp_i2c_drvdata *drvdata = platform_get_drvdata(pdev); + + pr_info("[%s] drvdata engine %d\n", __func__, drvdata->engine); + i2c_del_adapter(&drvdata->adapter); + + return 0; +} + +static const struct of_device_id gxp_i2c_of_match[] = { + { .compatible = "hpe,gxp-i2c" }, + {}, +}; +MODULE_DEVICE_TABLE(of, gxp_i2c_of_match); + +static struct platform_driver gxp_i2c_driver = { + .probe = gxp_i2c_probe, + .remove = gxp_i2c_remove, + .driver = { + .name = "gxp-i2c", + .of_match_table = gxp_i2c_of_match, + }, +}; +module_platform_driver(gxp_i2c_driver); + +MODULE_AUTHOR("Nick Hawkins "); +MODULE_DESCRIPTION("HPE GXP I2C bus driver"); +MODULE_LICENSE("GPL");