diff mbox series

[v3,13/14] rtc: pcf2127: add flag for watchdog register value read support

Message ID 20221215150214.1109074-14-hugo@hugovil.com
State New
Headers
Series rtc: pcf2127: add PCF2131 driver |

Commit Message

Hugo Villeneuve Dec. 15, 2022, 3:02 p.m. UTC 
  From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

The watchdog value register cannot be read on the PCF2131 after being
set.

Add a new flag to identify which variant has read access to this
register, and use this flag to selectively test if watchdog timer was
started by bootloader.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 drivers/rtc/rtc-pcf2127.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

Comments

Bruno Thomsen Jan. 7, 2023, 6:47 p.m. UTC | #1 
Den tor. 15. dec. 2022 kl. 16.19 skrev Hugo Villeneuve <hugo@hugovil.com>:
>
> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
>
> The watchdog value register cannot be read on the PCF2131 after being
> set.
>
> Add a new flag to identify which variant has read access to this
> register, and use this flag to selectively test if watchdog timer was
> started by bootloader.
>
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Reviewed-by: Bruno Thomsen <bruno.thomsen@gmail.com>

> ---
>  drivers/rtc/rtc-pcf2127.c | 20 ++++++++++++++------
>  1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
> index 3fd2fee4978b..1d2b5c9e6757 100644
> --- a/drivers/rtc/rtc-pcf2127.c
> +++ b/drivers/rtc/rtc-pcf2127.c
> @@ -214,6 +214,7 @@ struct pcf21xx_config {
>         int max_register;
>         unsigned int has_nvmem:1;
>         unsigned int has_bit_wd_ctl_cd0:1;
> +       unsigned int wd_val_reg_readable:1; /* If watchdog value register can be read. */
>         unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */
>         unsigned int has_reset_reg:1; /* If variant has a reset register. */
>         u8 regs_td_base; /* Time/data base registers. */
> @@ -511,7 +512,6 @@ static const struct watchdog_ops pcf2127_watchdog_ops = {
>
>  static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
>  {
> -       u32 wdd_timeout;
>         int ret;
>
>         if (!IS_ENABLED(CONFIG_WATCHDOG) ||
> @@ -539,12 +539,17 @@ static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
>         watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
>
>         /* Test if watchdog timer is started by bootloader */
> -       ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout);
> -       if (ret)
> -               return ret;
> +       if (pcf2127->cfg->wd_val_reg_readable) {
> +               u32 wdd_timeout;
> +
> +               ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
> +                                 &wdd_timeout);
> +               if (ret)
> +                       return ret;
>
> -       if (wdd_timeout)
> -               set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
> +               if (wdd_timeout)
> +                       set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
> +       }
>
>         return devm_watchdog_register_device(dev, &pcf2127->wdd);
>  }
> @@ -953,6 +958,7 @@ static struct pcf21xx_config pcf21xx_cfg[] = {
>                 .max_register = 0x1d,
>                 .has_nvmem = 1,
>                 .has_bit_wd_ctl_cd0 = 1,
> +               .wd_val_reg_readable = 1,
>                 .has_int_a_b = 0,
>                 .has_reset_reg = 0,
>                 .regs_td_base = PCF2127_REG_TIME_DATE_BASE,
> @@ -980,6 +986,7 @@ static struct pcf21xx_config pcf21xx_cfg[] = {
>                 .max_register = 0x19,
>                 .has_nvmem = 0,
>                 .has_bit_wd_ctl_cd0 = 0,
> +               .wd_val_reg_readable = 1,
>                 .has_int_a_b = 0,
>                 .has_reset_reg = 0,
>                 .regs_td_base = PCF2127_REG_TIME_DATE_BASE,
> @@ -1007,6 +1014,7 @@ static struct pcf21xx_config pcf21xx_cfg[] = {
>                 .max_register = 0x36,
>                 .has_nvmem = 0,
>                 .has_bit_wd_ctl_cd0 = 0,
> +               .wd_val_reg_readable = 0,
>                 .has_int_a_b = 1,
>                 .has_reset_reg = 1,
>                 .regs_td_base = PCF2131_REG_TIME_DATE_BASE,
> --
> 2.30.2
>
diff mbox series

Patch

diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 3fd2fee4978b..1d2b5c9e6757 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -214,6 +214,7 @@  struct pcf21xx_config {
 	int max_register;
 	unsigned int has_nvmem:1;
 	unsigned int has_bit_wd_ctl_cd0:1;
+	unsigned int wd_val_reg_readable:1; /* If watchdog value register can be read. */
 	unsigned int has_int_a_b:1; /* PCF2131 supports two interrupt outputs. */
 	unsigned int has_reset_reg:1; /* If variant has a reset register. */
 	u8 regs_td_base; /* Time/data base registers. */
@@ -511,7 +512,6 @@  static const struct watchdog_ops pcf2127_watchdog_ops = {
 
 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
 {
-	u32 wdd_timeout;
 	int ret;
 
 	if (!IS_ENABLED(CONFIG_WATCHDOG) ||
@@ -539,12 +539,17 @@  static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
 	watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
 
 	/* Test if watchdog timer is started by bootloader */
-	ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout);
-	if (ret)
-		return ret;
+	if (pcf2127->cfg->wd_val_reg_readable) {
+		u32 wdd_timeout;
+
+		ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val,
+				  &wdd_timeout);
+		if (ret)
+			return ret;
 
-	if (wdd_timeout)
-		set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
+		if (wdd_timeout)
+			set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
+	}
 
 	return devm_watchdog_register_device(dev, &pcf2127->wdd);
 }
@@ -953,6 +958,7 @@  static struct pcf21xx_config pcf21xx_cfg[] = {
 		.max_register = 0x1d,
 		.has_nvmem = 1,
 		.has_bit_wd_ctl_cd0 = 1,
+		.wd_val_reg_readable = 1,
 		.has_int_a_b = 0,
 		.has_reset_reg = 0,
 		.regs_td_base = PCF2127_REG_TIME_DATE_BASE,
@@ -980,6 +986,7 @@  static struct pcf21xx_config pcf21xx_cfg[] = {
 		.max_register = 0x19,
 		.has_nvmem = 0,
 		.has_bit_wd_ctl_cd0 = 0,
+		.wd_val_reg_readable = 1,
 		.has_int_a_b = 0,
 		.has_reset_reg = 0,
 		.regs_td_base = PCF2127_REG_TIME_DATE_BASE,
@@ -1007,6 +1014,7 @@  static struct pcf21xx_config pcf21xx_cfg[] = {
 		.max_register = 0x36,
 		.has_nvmem = 0,
 		.has_bit_wd_ctl_cd0 = 0,
+		.wd_val_reg_readable = 0,
 		.has_int_a_b = 1,
 		.has_reset_reg = 1,
 		.regs_td_base = PCF2131_REG_TIME_DATE_BASE,