From patchwork Tue Dec 13 23:01:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 32972 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:e747:0:0:0:0:0 with SMTP id c7csp409061wrn; Tue, 13 Dec 2022 15:02:36 -0800 (PST) X-Google-Smtp-Source: AA0mqf4TvrfVb/Cnm6QmHEgkacVGF9ekyK5y7OiM4mqqU7QGJi1LCQ5TToLQrLsCHUHs6jOUfIfV X-Received: by 2002:a05:6402:444b:b0:463:ba73:9139 with SMTP id o11-20020a056402444b00b00463ba739139mr19044651edb.2.1670972555962; Tue, 13 Dec 2022 15:02:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670972555; cv=none; d=google.com; s=arc-20160816; b=XpKov5pXDtrDn1ZlgiHJwD0ERs50g39sYXVAnHbWtsGN1YUphgjp4VKYOi4Z1QPpA4 aVRmhFwOrrY9Ami859S0a03k3fKdh82rAx2KRmT+r2zWEGzLV1RHRetqBFPRJ1pDfDjP O/RXzVywTFVlx5HySM3UTHRk9GPkB3IbwYzeg/8aeXbj3Prp1sSWG+EVCLraQSMiPDsr PQRmIQgtngPAFFNSOcwIuz4Lbp3RnyWiyfw11rg7xL8Cof/5JYMkxZ9Ngcnnr9okd7kk 3DAMDj/lr+BHBP1euI2nvtcHogQvAPQnEVvVgcBxRS+Tw1UHD8LNdK6Z/iP/Ta/W0C3p Ny4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=DJvSbgpXb89Qqy8MbB1O3yqpZ74WNiJeT67fdg6Xyko=; b=t9PcT4gA60eUM8jjY80gXbcPeR8yUSXUVfMVp/hVuy/LIHgUAPUWU4Lpifj1Ev57mV irT0F5i5JANKvSlfGZv5nYo1Fink/3oUMUIwPrj+CDQqlbXbuGYYTN9hhsVawxxtRS37 Sz0QzA5wuij/nlsB3maj9Q83pvK3W0PfYmNSM0TnKKP7q8NeGSDVDjsP+HqpoURE5lJ5 QL3D9GyYdYfAQFt+wr9A53K4F/YfeE8eg7giiTlvKwdsy9KGGV8KKbU3+APS++k+pgWt lQ4oL08BflGaMjx8MGRAZUMK/wm2OdQZmeZfOXR3T1vCWAtvFjOaVJVvhw/z3RFnmsSK vJfg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y9-20020a056402440900b0045d27c0ba90si12747361eda.577.2022.12.13.15.02.12; Tue, 13 Dec 2022 15:02:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236898AbiLMXBu (ORCPT + 99 others); Tue, 13 Dec 2022 18:01:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236801AbiLMXBq (ORCPT ); Tue, 13 Dec 2022 18:01:46 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4692EC2; Tue, 13 Dec 2022 15:01:45 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,242,1665414000"; d="scan'208";a="143231090" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 14 Dec 2022 08:01:44 +0900 Received: from mulinux.home (unknown [10.226.93.1]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id F23E6400D4F6; Wed, 14 Dec 2022 08:01:38 +0900 (JST) From: Fabrizio Castro To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Geert Uytterhoeven Cc: Phil Edworthy , Magnus Damm , Wolfram Sang , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Chris Paterson , Biju Das , Fabrizio Castro , Laurent Pinchart , Jacopo Mondi Subject: [PATCH 1/4] clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries Date: Tue, 13 Dec 2022 23:01:26 +0000 Message-Id: <20221213230129.549968-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221213230129.549968-1-fabrizio.castro.jz@renesas.com> References: <20221213230129.549968-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752141718845669024?= X-GMAIL-MSGID: =?utf-8?q?1752141718845669024?= From: Phil Edworthy Add SDHI/eMMC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy Reviewed-by: Geert Uytterhoeven --- This patch can clash with the below patch (which hasn't been reviewed yet): https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221212172804.1277751-2-biju.das.jz@bp.renesas.com/ drivers/clk/renesas/r9a09g011-cpg.c | 34 +++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index dd5e442ec4a9..8437b7d38e94 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -23,11 +23,14 @@ #define DIV_A DDIV_PACK(0x200, 0, 3) #define DIV_B DDIV_PACK(0x204, 0, 2) +#define DIV_D DDIV_PACK(0x204, 4, 2) #define DIV_E DDIV_PACK(0x204, 8, 1) #define DIV_W DDIV_PACK(0x328, 0, 3) #define SEL_B SEL_PLL_PACK(0x214, 0, 1) +#define SEL_D SEL_PLL_PACK(0x214, 1, 1) #define SEL_E SEL_PLL_PACK(0x214, 2, 1) +#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1) #define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1) enum clk_ids { @@ -50,11 +53,14 @@ enum clk_ids { CLK_PLL4, CLK_DIV_A, CLK_DIV_B, + CLK_DIV_D, CLK_DIV_E, CLK_DIV_W, CLK_SEL_B, CLK_SEL_B_D2, + CLK_SEL_D, CLK_SEL_E, + CLK_SEL_SDI, CLK_SEL_W0, /* Module Clocks */ @@ -81,6 +87,14 @@ static const struct clk_div_table dtable_divb[] = { {0, 0}, }; + +static const struct clk_div_table dtable_divd[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {0, 0}, +}; + static const struct clk_div_table dtable_divw[] = { {0, 6}, {1, 7}, @@ -94,8 +108,10 @@ static const struct clk_div_table dtable_divw[] = { /* Mux clock tables */ static const char * const sel_b[] = { ".main", ".divb" }; +static const char * const sel_d[] = { ".main", ".divd" }; static const char * const sel_e[] = { ".main", ".dive" }; static const char * const sel_w[] = { ".main", ".divw" }; +static const char * const sel_sdi[] = { ".main", ".pll2_200" }; static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { /* External Clock Inputs */ @@ -115,11 +131,14 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva), DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb), + DEF_DIV_RO(".divd", CLK_DIV_D, CLK_PLL2_200, DIV_D, dtable_divd), DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL), DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw), DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b), + DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d), DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e), + DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi), DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w), DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2), @@ -128,6 +147,18 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2), DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), + DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0), + DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1), + DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2), + DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3), + DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4), + DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5), + DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6), + DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7), + DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8), + DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9), + DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10), + DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11), DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), @@ -151,6 +182,9 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), + DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6), + DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7), + DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8), DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8),