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[2620:137:e000::1:20]) by mx.google.com with ESMTP id q27-20020a50aa9b000000b0046b807c1a06si9492492edc.350.2022.12.13.14.44.38; Tue, 13 Dec 2022 14:45:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236753AbiLMWnf (ORCPT + 99 others); Tue, 13 Dec 2022 17:43:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236039AbiLMWn0 (ORCPT ); Tue, 13 Dec 2022 17:43:26 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 29FF42127F; Tue, 13 Dec 2022 14:43:25 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,242,1665414000"; d="scan'208";a="146060114" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Dec 2022 07:43:24 +0900 Received: from mulinux.home (unknown [10.226.93.1]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2D13540F4527; Wed, 14 Dec 2022 07:43:18 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH 1/5] dt-bindings: gpio: Add RZ/V2M PWC GPIO driver bindings Date: Tue, 13 Dec 2022 22:43:06 +0000 Message-Id: <20221213224310.543243-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> References: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1752140613615163185?= X-GMAIL-MSGID: =?utf-8?q?1752140613615163185?= Add dt-bindings document for the RZ/V2M PWC GPIO driver. Signed-off-by: Fabrizio Castro --- .../bindings/gpio/renesas,rzv2m-pwc-gpio.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml b/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml new file mode 100644 index 000000000000..ecc034d53259 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/renesas,rzv2m-pwc-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) GPIO + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with General-Purpose + Output pins, alongside the below functions + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + This node uses syscon to map the register used to control the GPIOs + (the register map is retrieved from the parent dt-node), and the node should + be represented as a sub node of a "syscon", "simple-mfd" node. + +maintainers: + - Fabrizio Castro + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc-gpio # RZ/V2M + - renesas,r9a09g055-pwc-gpio # RZ/V2MA + - const: renesas,rzv2m-pwc-gpio + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Offset in the register map for controlling the GPIOs (in bytes). + + regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the register map node. + + gpio-controller: true + + '#gpio-cells': + const: 2 + +required: + - compatible + - regmap + - offset + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + gpio { + compatible = "renesas,r9a09g011-pwc-gpio", + "renesas,rzv2m-pwc-gpio"; + regmap = <®mapnode>; + offset = <0x80>; + gpio-controller; + #gpio-cells = <2>; + };