[v4] arm64: dts: qcom: sa8540p-ride: enable pcie2a node
Commit Message
Add the pcie2a, pcie2a_phy, and respective tlmm
nodes that are needed to get pcie 2a controller
enabled on Qdrive3.
This patch enables 4GB 64bit memory space for
PCIE_2A to have BAR allocations of 64bit pref mem
needed on this Qdrive3 platform with dual SoCs
for root port and switch NT-EP. Hence this ranges
property is overridden in sa8540p-ride.dts only.
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reported-by: kernel test robot <lkp@intel.com>
---
Changes since v3:
- Fix syntax error and add Reported-by (Kernel test robot)
Changes since v2:
- Discard below patch as v3 is merged in qcom tree
[v4] arm64: dts: qcom: sa8540p-ride: enable PCIe support
https://lore.kernel.org/all/20221206161916.315640-1-bmasney@redhat.com/
- Move tlmm PINCTRL to the end and add R-b (Brian)
Changes since v1:
- Fix ranges property indentation (Konrad)
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 96 +++++++++++++++++------
1 file changed, 71 insertions(+), 25 deletions(-)
Comments
On 13/12/2022 06:11, Shazad Hussain wrote:
> Add the pcie2a, pcie2a_phy, and respective tlmm
> nodes that are needed to get pcie 2a controller
> enabled on Qdrive3.
>
> This patch enables 4GB 64bit memory space for
> PCIE_2A to have BAR allocations of 64bit pref mem
> needed on this Qdrive3 platform with dual SoCs
> for root port and switch NT-EP. Hence this ranges
> property is overridden in sa8540p-ride.dts only.
>
> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
> Reviewed-by: Brian Masney <bmasney@redhat.com>
> Reported-by: kernel test robot <lkp@intel.com>
Drop, robot did not report this patch.
> ---
> Changes since v3:
> - Fix syntax error and add Reported-by (Kernel test robot)
So the previous patch was not even build... thus 100% not tested. Is
this one at least built?
Best regards,
Krzysztof
On 12/13/2022 1:31 PM, Krzysztof Kozlowski wrote:
> On 13/12/2022 06:11, Shazad Hussain wrote:
>> Add the pcie2a, pcie2a_phy, and respective tlmm
>> nodes that are needed to get pcie 2a controller
>> enabled on Qdrive3.
>>
>> This patch enables 4GB 64bit memory space for
>> PCIE_2A to have BAR allocations of 64bit pref mem
>> needed on this Qdrive3 platform with dual SoCs
>> for root port and switch NT-EP. Hence this ranges
>> property is overridden in sa8540p-ride.dts only.
>>
>> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
>> Reviewed-by: Brian Masney <bmasney@redhat.com>
>> Reported-by: kernel test robot <lkp@intel.com>
>
> Drop, robot did not report this patch.
>
You mean I should keep only Kernel test as Reported by ?
>> ---
>> Changes since v3:
>> - Fix syntax error and add Reported-by (Kernel test robot)
>
> So the previous patch was not even build... thus 100% not tested. Is
> this one at least built?
>
I built that, but after running checkpatch with --fix, I think it
dropped the closing brace of tlmm. My bad :|
Yes, v4 is compiled and 100% tested.
-Shazad
> Best regards,
> Krzysztof
>
On 13/12/2022 09:05, Shazad Hussain wrote:
>
>
> On 12/13/2022 1:31 PM, Krzysztof Kozlowski wrote:
>> On 13/12/2022 06:11, Shazad Hussain wrote:
>>> Add the pcie2a, pcie2a_phy, and respective tlmm
>>> nodes that are needed to get pcie 2a controller
>>> enabled on Qdrive3.
>>>
>>> This patch enables 4GB 64bit memory space for
>>> PCIE_2A to have BAR allocations of 64bit pref mem
>>> needed on this Qdrive3 platform with dual SoCs
>>> for root port and switch NT-EP. Hence this ranges
>>> property is overridden in sa8540p-ride.dts only.
>>>
>>> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
>>> Reviewed-by: Brian Masney <bmasney@redhat.com>
>>> Reported-by: kernel test robot <lkp@intel.com>
>>
>> Drop, robot did not report this patch.
>>
>
> You mean I should keep only Kernel test as Reported by ?
No, I mean entire line should be removed. This robot did not report
missing feature/bug thus there is no credit for him for creating this patch.
>
>>> ---
>>> Changes since v3:
>>> - Fix syntax error and add Reported-by (Kernel test robot)
>>
>> So the previous patch was not even build... thus 100% not tested. Is
>> this one at least built?
>>
>
> I built that, but after running checkpatch with --fix, I think it
> dropped the closing brace of tlmm. My bad :|
Please do not send patches with checkpatch --fix, without prior testing
the patch. Not the code, but the patch. By testing patch I mean checking
different mainline branch, applying the mbox/patch (git am) and
comparing with git diff.
Best regards,
Krzysztof
On Tue, Dec 13, 2022 at 10:41:08AM +0530, Shazad Hussain wrote:
> Add the pcie2a, pcie2a_phy, and respective tlmm
> nodes that are needed to get pcie 2a controller
> enabled on Qdrive3.
>
> This patch enables 4GB 64bit memory space for
> PCIE_2A to have BAR allocations of 64bit pref mem
> needed on this Qdrive3 platform with dual SoCs
> for root port and switch NT-EP. Hence this ranges
> property is overridden in sa8540p-ride.dts only.
Please break your lines at 72 columns or so (not 50).
> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
> Reviewed-by: Brian Masney <bmasney@redhat.com>
> Reported-by: kernel test robot <lkp@intel.com>
No need for this Reported-by (even if some people may disagree).
> ---
> Changes since v3:
> - Fix syntax error and add Reported-by (Kernel test robot)
>
> Changes since v2:
> - Discard below patch as v3 is merged in qcom tree
> [v4] arm64: dts: qcom: sa8540p-ride: enable PCIe support
> https://lore.kernel.org/all/20221206161916.315640-1-bmasney@redhat.com/
> - Move tlmm PINCTRL to the end and add R-b (Brian)
>
> Changes since v1:
> - Fix ranges property indentation (Konrad)
>
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 96 +++++++++++++++++------
> 1 file changed, 71 insertions(+), 25 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> index 6c547f1b13dc..d70859803fbd 100644
> --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
> @@ -146,6 +146,27 @@ vreg_l8g: ldo8 {
> };
> };
>
> +&pcie2a {
> + ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
> + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
> + <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>;
> +
> + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie2a_default>;
> +
> + status = "okay";
> +};
> +
> +&pcie2a_phy {
> + vdda-phy-supply = <&vreg_l11a>;
> + vdda-pll-supply = <&vreg_l3a>;
> +
> + status = "okay";
> +};
> +
> &pcie3a {
> ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
> @@ -186,31 +207,6 @@ &remoteproc_nsp1 {
> status = "okay";
> };
>
> -&tlmm {
> - pcie3a_default: pcie3a-default-state {
> - perst-pins {
> - pins = "gpio151";
> - function = "gpio";
> - drive-strength = <2>;
> - bias-pull-down;
> - };
> -
> - clkreq-pins {
> - pins = "gpio150";
> - function = "pcie3a_clkreq";
> - drive-strength = <2>;
> - bias-pull-up;
> - };
> -
> - wake-pins {
> - pins = "gpio56";
> - function = "gpio";
> - drive-strength = <2>;
> - bias-pull-up;
> - };
> - };
> -};
> -
This is a separate change which should go in its own patch. (We sometimes
make exceptions to this general rule, but then you must least mention
that you're also moving the tlmm nodes and why you're doing so in the
commit message.)
> &ufs_mem_hc {
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
>
> @@ -268,3 +264,53 @@ &usb_2_qmpphy0 {
> &xo_board_clk {
> clock-frequency = <38400000>;
> };
> +
> +/* PINCTRL */
> +
> +&tlmm {
Johan
@@ -146,6 +146,27 @@ vreg_l8g: ldo8 {
};
};
+&pcie2a {
+ ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
+ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
+ <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>;
+
+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2a_default>;
+
+ status = "okay";
+};
+
+&pcie2a_phy {
+ vdda-phy-supply = <&vreg_l11a>;
+ vdda-pll-supply = <&vreg_l3a>;
+
+ status = "okay";
+};
+
&pcie3a {
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
@@ -186,31 +207,6 @@ &remoteproc_nsp1 {
status = "okay";
};
-&tlmm {
- pcie3a_default: pcie3a-default-state {
- perst-pins {
- pins = "gpio151";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- clkreq-pins {
- pins = "gpio150";
- function = "pcie3a_clkreq";
- drive-strength = <2>;
- bias-pull-up;
- };
-
- wake-pins {
- pins = "gpio56";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
-
&ufs_mem_hc {
reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
@@ -268,3 +264,53 @@ &usb_2_qmpphy0 {
&xo_board_clk {
clock-frequency = <38400000>;
};
+
+/* PINCTRL */
+
+&tlmm {
+ pcie2a_default: pcie2a-default-state {
+ perst-pins {
+ pins = "gpio143";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio142";
+ function = "pcie2a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio145";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie3a_default: pcie3a-default-state {
+ perst-pins {
+ pins = "gpio151";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio150";
+ function = "pcie3a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio56";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};