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From: <patrice.chotard@foss.st.com>
To: <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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CC: <mcoquelin.stm32@gmail.com>,
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Alexandre Torgue <alexandre.torgue@st.com>
Subject: [PATCH 3/4] ARM: dts: stm32: Fix qspi pinctrl phandle for
stm32mp157c-emstamp-argon
Date: Mon, 12 Dec 2022 09:51:41 +0100
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| Series |
Fix qspi pinctrl phandle for stm3mp15 based boards
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Commit Message
Patrice CHOTARD
Dec. 12, 2022, 8:51 a.m. UTC
From: Patrice Chotard <patrice.chotard@foss.st.com> Chip select pinctrl phandle was missing in several stm32mp15x based boards. Fixes: ea99a5a02ebc ("ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi) Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Reinhold Mueller <reinhold.mueller@emtrion.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi index 30156b7546ed..d540550f7da2 100644 --- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -391,8 +391,12 @@ &pwr_regulators { &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>;