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[2.34.28.158]) by smtp.gmail.com with ESMTPSA id dt26-20020a05620a479a00b006fbf88667bcsm29484qkb.77.2022.12.09.07.29.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 07:29:26 -0800 (PST) From: Marco Pagani To: Dinh Nguyen , Michael Turquette , Stephen Boyd Cc: Marco Pagani , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling Date: Fri, 9 Dec 2022 16:29:11 +0100 Message-Id: <20221209152913.1335068-5-marpagan@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209152913.1335068-1-marpagan@redhat.com> References: <20221209152913.1335068-1-marpagan@redhat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751750917263050843?= X-GMAIL-MSGID: =?utf-8?q?1751751019495786085?= The function of_clk_add_provider() has been deprecated, so use its suggested replacement of_clk_add_hw_provider() instead. Since of_clk_add_hw_provider() can fail, like of_clk_add_provider(), check its return value and do the error handling. The indentation of the init function parameters has been aligned to match open parenthesis as suggested by checkpatch. Signed-off-by: Marco Pagani --- drivers/clk/socfpga/clk-gate-a10.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index 7cdf2f07c79b..06f129c160bc 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -40,7 +40,7 @@ static struct clk_ops gateclk_ops = { }; static void __init __socfpga_gate_init(struct device_node *node, - const struct clk_ops *ops) + const struct clk_ops *ops) { u32 clk_gate[2]; u32 div_reg[3]; @@ -94,13 +94,25 @@ static void __init __socfpga_gate_init(struct device_node *node, socfpga_clk->hw.hw.init = &init; hw_clk = &socfpga_clk->hw.hw; - if (clk_hw_register(NULL, hw_clk)) { - kfree(socfpga_clk); - return; + rc = clk_hw_register(NULL, hw_clk); + if (rc) { + pr_err("Could not register clock:%s\n", clk_name); + goto err_clk_hw_register; } - rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); - if (WARN_ON(rc)) - return; + + rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk); + if (rc) { + pr_err("Could not register clock provider for node:%s\n", + clk_name); + goto err_of_clk_add_hw_provider; + } + + return; + +err_of_clk_add_hw_provider: + clk_hw_unregister(hw_clk); +err_clk_hw_register: + kfree(socfpga_clk); } void __init socfpga_a10_gate_init(struct device_node *node)