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( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 09 Dec 2022 23:04:44 +0800 (CST) X-QQ-SSF: 01200000002000B0C000B00A0000000 X-QQ-FEAT: eSZ1CZgv+JDxI3bkYMKbTdjkw3HK7jXPhTCSg7Rm3gGAzVEQh3qZVDk772x62 RcnlQ3TCDQBKpL4HEXYtAYBq+s10VpGHenajCYPlmnRYkDW1cCyvU28bP3dGoFJzt/NnAAi 9pbziDhkypc8rcrRB2SXSoQ9okkCAjY0JDno58pfyZqblYWybP98pprywYy6WnA30twSSkk HtUjsUs0pEf3XziNrqPZPNwjWhRxgNggsCplY7mQcxnOAKQawZmsOycyzYMOeAirqYRIVT6 f0vj/eey25M+7iykhR5ifMsDFZiAAyU+ULt91TPKJ7Y3MhD+QWQEG0xfqPE7M5sWLXpuFjU BkP38Blu5oPle1WhiJqDtKkDcUCCyCD7fzWHdV0BNU0Wonfe/4= X-QQ-GoodBg: 0 From: Bin Meng To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org Cc: Albert Ou , Greg Kroah-Hartman , Jiri Slaby , Palmer Dabbelt , Paul Walmsley Subject: [PATCH v3 2/3] riscv: Implement semihost.h for earlycon semihost driver Date: Fri, 9 Dec 2022 23:04:36 +0800 Message-Id: <20221209150437.795918-3-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221209150437.795918-1-bmeng@tinylab.org> References: <20221209150437.795918-1-bmeng@tinylab.org> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751749614209776172?= X-GMAIL-MSGID: =?utf-8?q?1751749614209776172?= Per RISC-V semihosting spec [1], implement semihost.h for the existing Arm semihosting earlycon driver to work on RISC-V. Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1] Signed-off-by: Bin Meng --- Changes in v3: - add #ifdef in the header to prevent from multiple inclusion - add forward-declare struct uart_port - add a Link tag in the commit message Changes in v2: - Move the RISC-V implementation to semihost.h arch/riscv/include/asm/semihost.h | 26 ++++++++++++++++++++++++++ drivers/tty/serial/Kconfig | 2 +- 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/semihost.h diff --git a/arch/riscv/include/asm/semihost.h b/arch/riscv/include/asm/semihost.h new file mode 100644 index 000000000000..557a34938193 --- /dev/null +++ b/arch/riscv/include/asm/semihost.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 tinylab.org + * Author: Bin Meng + */ + +#ifndef _RISCV_SEMIHOST_H_ +#define _RISCV_SEMIHOST_H_ + +struct uart_port; + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("addi a1, %0, 0\n" + "addi a0, zero, 3\n" + ".balign 16\n" + ".option push\n" + ".option norvc\n" + "slli zero, zero, 0x1f\n" + "ebreak\n" + "srai zero, zero, 0x7\n" + ".option pop\n" + : : "r" (&c) : "a0", "a1", "memory"); +} + +#endif /* _RISCV_SEMIHOST_H_ */ diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 434f83168546..e94d1265151c 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -75,7 +75,7 @@ config SERIAL_AMBA_PL011_CONSOLE config SERIAL_EARLYCON_ARM_SEMIHOST bool "Early console using ARM semihosting" - depends on ARM64 || ARM + depends on ARM64 || ARM || RISCV select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON