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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , "Konrad Rzeszutek Wilk" , Paolo Bonzini , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , Alexey Kardashevskiy , , , Subject: [PATCH v5 5/7] x86/cpu: Define a scattered AMD Automatic IBRS feature bit Date: Mon, 5 Dec 2022 17:32:33 -0600 Message-ID: <20221205233235.622491-6-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221205233235.622491-1-kim.phillips@amd.com> References: <20221205233235.622491-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E642:EE_|DS7PR12MB6047:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f942405-8a98-4279-5097-08dad7192c85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AygsS7zrbhx63L3ni1zkabrZjyrScZAVKbj+drg52qs/FHjDnMgJHL/qlhNiBO+RvIgMgBftUnwWSQ+LFq8wcOJq8Bb+efPb9nxjMAy2eMTJGUacMDtrKTed5N615aw7vTaEJtFQ85Q/eTINJeXRFHpHIwi1+flfHMCXcI22Y9TTfIgLJd7Nxyq2k/kHyRWWe3gtnmuAObPP22dLd+FlIunJFwRLZgG9uyOweStEdG8eOSqEVrByE/HZiUWqnXJpktMHGkRM/r/w7bowqkq0EQWiM6ggwAX5CiSXW2FuFhetX6VOZZ8hPefQ7q73WumUMiuiIK4ux1KnvyAcdR3mh+w9p5g/6xXEtXY0xiDrcWuQGYIySvu2TCbRLV6pVDdK4cTPA30zrDCnEDNJMnjcQufR5APHsrPO4ZXv+i2DijT3LH4s7LJF9vwPo5dW8wiAgHi4x6WHDGRlTyDTzjEy/5dmObrK7BFOwb/oSmau/34ZJbnu3VH2nrYsfn+7NTUbFWXCHLXILg24TVX0Thc+e1EHvMrIJEMUtYK+RKJkP5akcZXz0AC90EklEzUmjE0o0NZHkedN8UXPDx+HTdXtMjGaxKNV5AZfYGwdmMw84nBsoD7PD748PBIr4ZxSSIeLKZvdD3FecXp26INIyG2gjFZyMK2SSWWpWL1ang/qaKbGPZPFdgW33Gd/FLgGEG4tjSQBXG9KF+8MbcA/NzoS3kvVzmia5lhnhJzrZZ/MFQk= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(39860400002)(396003)(376002)(451199015)(40470700004)(36840700001)(46966006)(2906002)(7416002)(8936002)(44832011)(8676002)(4326008)(36756003)(336012)(86362001)(81166007)(356005)(186003)(16526019)(47076005)(2616005)(82310400005)(426003)(70206006)(1076003)(41300700001)(82740400003)(5660300002)(316002)(6916009)(26005)(7696005)(54906003)(6666004)(36860700001)(70586007)(40460700003)(478600001)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 23:33:54.6653 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f942405-8a98-4279-5097-08dad7192c85 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E642.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6047 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751419029590616456?= X-GMAIL-MSGID: =?utf-8?q?1751419029590616456?= It's bit 8 of the hardware CPUID 0x80000021 EAX leaf. Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 5ddde18c1ae8..961eb49532b7 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -309,6 +309,7 @@ #define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ #define X86_FEATURE_NO_NESTED_DATA_BP (11*32+21) /* "" AMD No Nested Data Breakpoints */ #define X86_FEATURE_NULL_SEL_CLR_BASE (11*32+22) /* "" AMD Null Selector Clears Base */ +#define X86_FEATURE_AUTOIBRS (11*32+23) /* AMD Automatic IBRS */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index caa03466cd9e..7ae7203cd410 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -48,6 +48,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_NO_NESTED_DATA_BP,CPUID_EAX, 0, 0x80000021, 0 }, { X86_FEATURE_LFENCE_RDTSC, CPUID_EAX, 2, 0x80000021, 0 }, { X86_FEATURE_NULL_SEL_CLR_BASE,CPUID_EAX, 6, 0x80000021, 0 }, + { X86_FEATURE_AUTOIBRS, CPUID_EAX, 8, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 }