From patchwork Mon Dec 5 05:00:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 29526 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2071810wrr; Sun, 4 Dec 2022 21:07:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf44aE9JNj5897zGckg2lE1OJMSS7ZCuJRfhHX/YykBL7PmcqoKMxkLSgp/k+Rw2Yns5U46C X-Received: by 2002:aa7:db90:0:b0:459:aa70:d4fd with SMTP id u16-20020aa7db90000000b00459aa70d4fdmr69907992edt.162.1670216858611; Sun, 04 Dec 2022 21:07:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670216858; cv=none; d=google.com; s=arc-20160816; b=FaJPV5xC6TXv6KCEiWvdygMuuOus15MZ3y4GDHs0i4ieInODpYxaoUWrZxw0tps9H4 /G9GpBpVibqwfyCIfOrboCm3294gteeIFCVjWwCgm50S4mx1K/FslqmGv8wyepzbseM8 IItL5V28dgNkd/OW8M4hkljOL+XNQgSXG3ZsbRbGdP+X4k9CiRdGavqAbWEgm7NhZL7B MgPvy/QIcwn0ZNFHBEwk43Wc4z0/ZEVGJVbTWv5KRWSj0ISu0kehq98SuTOg7/+YEx8V YNTc3gG6KzBleGL5tSufgkU/86PtFyklg2BW/X3X2jDHkrxr9Txh1StVZdGP11YsI2Qb Yd0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:feedback-id:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from; bh=tVTZXbwGKUPIH6bXQzct8CmW3mbSVTvYSdzRYt0n6ew=; b=oxGoaXgrxjI3ql25mFCuXfxCvWaTFobcSE+o0UuJ2bhJ4eSYFVX3Ox74ACzKAH9swn Dr3ay/LUOZ7vo7LPWylq8TC837sjiCUFRp+WlWKMHw6SLuANhxJQeyKirCPNj1STeyJX 12c8HmR+jS3okndf/9xe4v2JGymolQPBM6A3r7iE42n9AF21tBjKz4B+fWjBBE31ny3Y R2rNcGWxytijF503D9Qf1JvIwsD1eVQXFTP15JKbi2Yycbrh04MLFnPH8XcYjLyEcNu8 l2SutXxdLChl3QVcFyLumQ7J3t+4zhG2YL8ml5F6bWphHxNZpuTy50ny+e8lZAlf/htN Ivuw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id wz13-20020a170906fe4d00b007813b1924ccsi11171697ejb.934.2022.12.04.21.07.15; Sun, 04 Dec 2022 21:07:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231450AbiLEFBH (ORCPT + 99 others); Mon, 5 Dec 2022 00:01:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230327AbiLEFBG (ORCPT ); Mon, 5 Dec 2022 00:01:06 -0500 Received: from bg4.exmail.qq.com (bg4.exmail.qq.com [43.155.67.158]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11735F007; Sun, 4 Dec 2022 21:01:01 -0800 (PST) X-QQ-mid: bizesmtp83t1670216440tdylbiir Received: from ubuntu.. ( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 05 Dec 2022 13:00:39 +0800 (CST) X-QQ-SSF: 01200000000000B0B000000A0000000 X-QQ-FEAT: PsQCk6chbj5eK9ByDZQ9MzbRQ+lBTauZ/hMtMvyxFIKaWgsW4FUHY+4JhPLWp N8cebpF9TczECdys04OEy9HJn9oZa3VLtz3WoQfuUwnGABxRVV92ZnKGLKSiUNXJ5vOly2i EmIlXEJEYBtM4ApVe9usMvY0zPi/qFYgvjmCUU+0nd4O1v/vE9Ch275x3rBjfwiHDf3A2T1 ALae+DDCvEXhohsbyENwZm6hzz3JChV1omL5zQ9O6OghO903vD0KT3kQqoUEiDhoenU0Bhw fitqzjEco1KqPtDZACKdNQMZ2GeNH3iCax7PxJS9Eqz/Xv5K1uxwzC+K3OLB1vn9HYngpfU +ZkRbjl7WKf7o7fqqO6e0i0kHY+jg== X-QQ-GoodBg: 0 From: Bin Meng To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org Cc: Albert Ou , Greg Kroah-Hartman , Jiri Slaby , Palmer Dabbelt , Paul Walmsley Subject: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V Date: Mon, 5 Dec 2022 13:00:37 +0800 Message-Id: <20221205050038.195746-1-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751349312442216161?= X-GMAIL-MSGID: =?utf-8?q?1751349312442216161?= Per RISC-V semihosting spec [1], adapt the existing Arm semihosting earlycon driver to RISC-V. [1] https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Bin Meng --- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/earlycon-arm-semihost.c | 17 ++++++++++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 434f83168546..e94d1265151c 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -75,7 +75,7 @@ config SERIAL_AMBA_PL011_CONSOLE config SERIAL_EARLYCON_ARM_SEMIHOST bool "Early console using ARM semihosting" - depends on ARM64 || ARM + depends on ARM64 || ARM || RISCV select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c index fcdec5f42376..25a0f91926a3 100644 --- a/drivers/tty/serial/earlycon-arm-semihost.c +++ b/drivers/tty/serial/earlycon-arm-semihost.c @@ -6,6 +6,10 @@ * Adapted for ARM and earlycon: * Copyright (C) 2014 Linaro Ltd. * Author: Rob Herring + * + * Adapted for RISC-V and earlycon: + * Copyright (C) 2022 tinylab.org + * Author: Bin Meng */ #include #include @@ -23,7 +27,18 @@ */ static void smh_putc(struct uart_port *port, unsigned char c) { -#ifdef CONFIG_ARM64 +#if defined(CONFIG_RISCV) + asm volatile("addi a1, %0, 0\n" + "addi a0, zero, 3\n" + ".balign 16\n" + ".option push\n" + ".option norvc\n" + "slli zero, zero, 0x1f\n" + "ebreak\n" + "srai zero, zero, 0x7\n" + ".option pop\n" + : : "r" (&c) : "a0", "a1", "memory"); +#elif defined(CONFIG_ARM64) asm volatile("mov x1, %0\n" "mov x0, #3\n" "hlt 0xf000\n"