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[75.76.18.234]) by smtp.gmail.com with ESMTPSA id x1-20020ac84d41000000b0039a610a04b1sm4122237qtv.37.2022.12.02.05.55.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Dec 2022 05:55:46 -0800 (PST) From: Nathan Barrett-Morrison Cc: nathan.morrison@timesys.com, greg.malysa@timesys.com, Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org (open list:SPI NOR SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 3/3] mtd: spi-nor: Add support for IS25LX256 operating in 1S-8S-8S octal read mode Date: Fri, 2 Dec 2022 08:55:39 -0500 Message-Id: <20221202135539.271936-4-nathan.morrison@timesys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221202135539.271936-1-nathan.morrison@timesys.com> References: <20221202135539.271936-1-nathan.morrison@timesys.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751111308725400560?= X-GMAIL-MSGID: =?utf-8?q?1751111308725400560?= This adds the IS25LX256 chip into the ISSI flash_info parts table Signed-off-by: Nathan Barrett-Morrison Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/issi.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 89a66a19d754..362bc3603d8f 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -29,6 +29,35 @@ static const struct spi_nor_fixups is25lp256_fixups = { .post_bfpt = is25lp256_post_bfpt_fixups, }; +static int +is25lx256_post_bfpt_fixups(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt) +{ + /* + * IS25LX256 supports both 1S-1S-8S and 1S-8S-8S. + * However, the BFPT does not contain any information denoting this + * functionality, so the proper fast read opcodes are never setup. + * We're correcting this issue via the fixup below. Page program + * commands are detected and setup properly via the 4BAIT lookup. + */ + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8], + 0, 8, SPINOR_OP_READ_1_1_8, + SNOR_PROTO_1_1_8); + + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8; + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_8_8], + 0, 16, SPINOR_OP_READ_1_8_8, + SNOR_PROTO_1_8_8); + + return 0; +} + +static const struct spi_nor_fixups is25lx256_fixups = { + .post_bfpt = is25lx256_post_bfpt_fixups, +}; + static void pm25lv_nor_late_init(struct spi_nor *nor) { struct spi_nor_erase_map *map = &nor->params->erase_map; @@ -74,6 +103,9 @@ static const struct flash_info issi_nor_parts[] = { NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) .fixups = &is25lp256_fixups }, + { "is25lx256", INFO(0x9d5a19, 0, 0, 0) + PARSE_SFDP + .fixups = &is25lx256_fixups }, /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2)