From patchwork Fri Dec 2 09:49:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edmund Berenson X-Patchwork-Id: 28834 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp742994wrr; Fri, 2 Dec 2022 01:59:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf6skORiScMmg+dJHbaGSVM5TuRvDqGOfg1EuKjcDxnPKx9OyXb6VaDNFdBrXmxWeZQeLTJJ X-Received: by 2002:a17:906:52c8:b0:7ad:ba1e:1bac with SMTP id w8-20020a17090652c800b007adba1e1bacmr59723386ejn.528.1669975151482; Fri, 02 Dec 2022 01:59:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669975151; cv=none; d=google.com; s=arc-20160816; b=oGlh4gtiILcAq/0hlA2TWN3XSWHs+oD7WMKjHFK9h/a5xXCsyZ9JCVb7nFf68OQe6Z hNBKylFrCFg59/vEW4LKLBaY2QpwDa8999cRfSUyb++Vcc4Sip5/jwNiY5WRo1d9yGnX BSyFVZGfNZkS7Y/HLPjPlajDj2kVOB77vCAQXdaq3ya/pIr0a19kBLAMRynHOhtkC/kF M8q0rkkGJ6tO9LF2pdvp8hGH/wzAYcq2B+BKKtf4TsEssCRspzyj1ruWQD45+qE08ccu 3ZOCij2Ro6NGtACV4XF/SYlYMpPwpFAHqvIPiKdMeM2VqZUKTnWIpDV27l/s/fo0ZCoO zLCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :message-id:date:subject:cc:from; bh=im2rRR5PJvk82DFIGFS4nynO0MOwr166wWWAaXSEtaA=; b=nPEvqA8Aduz+xNOEt7HuXFV/ovQP/O6fsoukf9PVZ2A+2bs1g6pjT0G06xxwNTk7+Z L7HXeba9HD7P54lCSkwryFlKW7qzebslIAGSY9MAmO0qjEooJQQhgJtEA54YU6VdJZcF VjFHpGAQXeWN60JIIQZVXttAxg99PnY1WjOeSZQ7cQcn3VofOseKR80vrfZj6TAGLJwg Pca0XOvY3k8VAoIfdG8Pp3ek4rvR4aP59IcrllU5tXk30uj+6SuUYS2ikupSr6U2W6so 7jk7pZAO/IPB6o+2gQ0ZProUysvd+4qyNvhWzXkhKPeISecHKOmaFQ4jJ3hmjLX7SGQF Jt+w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id sd35-20020a1709076e2300b007ae52a5707bsi6821073ejc.95.2022.12.02.01.58.46; Fri, 02 Dec 2022 01:59:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233155AbiLBJtr (ORCPT + 99 others); Fri, 2 Dec 2022 04:49:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232887AbiLBJtj (ORCPT ); Fri, 2 Dec 2022 04:49:39 -0500 Received: from mx1.emlix.com (mx1.emlix.com [136.243.223.33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 228C6C934F for ; Fri, 2 Dec 2022 01:49:37 -0800 (PST) Received: from mailer.emlix.com (p5098be52.dip0.t-ipconnect.de [80.152.190.82]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.emlix.com (Postfix) with ESMTPS id C60E05FF10; Fri, 2 Dec 2022 10:49:35 +0100 (CET) From: Edmund Berenson Cc: Edmund Berenson , Lukasz Zemla , Serge Semin , Mark Brown , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] spi: dw: Write chip configuration before cs is set Date: Fri, 2 Dec 2022 10:49:34 +0100 Message-Id: <20221202094934.9420-1-edmund.berenson@emlix.com> X-Mailer: git-send-email 2.37.4 MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751095864079685076?= X-GMAIL-MSGID: =?utf-8?q?1751095864079685076?= Using chips with different cpol, causes first communication to fail on cpol change. To avoid this issue write cr0 register before cs is set. Suggested-by: Lukasz Zemla Signed-off-by: Edmund Berenson --- drivers/spi/spi-dw-core.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 57c9e384d6d4..c3da4fe3e510 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -93,6 +93,7 @@ static inline void dw_spi_debugfs_remove(struct dw_spi *dws) void dw_spi_set_cs(struct spi_device *spi, bool enable) { struct dw_spi *dws = spi_controller_get_devdata(spi->controller); + struct dw_spi_chip_data *chip = spi_get_ctldata(spi); bool cs_high = !!(spi->mode & SPI_CS_HIGH); u8 enable_cs = 0; @@ -106,8 +107,13 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable) * Enable register no matter whether the SPI core is configured to * support active-high or active-low CS level. */ - if (cs_high == enable) + if (cs_high == enable) { + dw_spi_enable_chip(dws, 0); + dw_writel(dws, DW_SPI_CTRLR0, chip->cr0); + dw_spi_enable_chip(dws, 1); + dw_writel(dws, DW_SPI_SER, BIT(enable_cs)); + } else dw_writel(dws, DW_SPI_SER, 0); }