diff mbox series

[v8,05/11] clk: meson: pll: export meson_clk_pll_wait_lock symbol

Message ID 20221201225703.6507-6-ddrokosov@sberdevices.ru
State New
Headers
Series add Amlogic A1 clock controller drivers |

Commit Message

Dmitry Rokosov Dec. 1, 2022, 10:56 p.m. UTC 
  Modern meson PLL IPs are a little bit different from early known PLLs.
The main difference is located in the init/enable/disable sequences; the
rate logic is the same. So drivers for the new PLLs can be inherited
from the clk-pll driver and redefine init/enable/disable routines only.
For that purpose we need to have meson_clk_pll_wait_lock() in the export
symbols list, because each lock operation should be ended with wait
cycles.

Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
---
 drivers/clk/meson/clk-pll.c | 3 ++-
 drivers/clk/meson/clk-pll.h | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 9e55617bc3b4..81c810d57a48 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -273,7 +273,7 @@  static int meson_clk_pll_determine_rate(struct clk_hw *hw,
 	return 0;
 }
 
-static int meson_clk_pll_wait_lock(struct clk_hw *hw)
+int meson_clk_pll_wait_lock(struct clk_hw *hw)
 {
 	struct clk_regmap *clk = to_clk_regmap(hw);
 	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
@@ -289,6 +289,7 @@  static int meson_clk_pll_wait_lock(struct clk_hw *hw)
 
 	return -ETIMEDOUT;
 }
+EXPORT_SYMBOL_GPL(meson_clk_pll_wait_lock);
 
 static int meson_clk_pll_init(struct clk_hw *hw)
 {
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index 367efd0f6410..85fec18c4b8a 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -47,4 +47,6 @@  extern const struct clk_ops meson_clk_pll_ro_ops;
 extern const struct clk_ops meson_clk_pll_ops;
 extern const struct clk_ops meson_clk_pcie_pll_ops;
 
+int meson_clk_pll_wait_lock(struct clk_hw *hw);
+
 #endif /* __MESON_CLK_PLL_H */