From patchwork Thu Dec 1 19:57:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 28536 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp458486wrr; Thu, 1 Dec 2022 12:01:48 -0800 (PST) X-Google-Smtp-Source: AA0mqf5RcbrD+wrnkDUkUyeWg8pjfGDOiEFuFYQiYeGKlfLO3sGsRBPtL2Z5KpnZBtifKRCXnhTZ X-Received: by 2002:a17:907:77d6:b0:78d:e26f:bfd8 with SMTP id kz22-20020a17090777d600b0078de26fbfd8mr57717969ejc.482.1669924908723; Thu, 01 Dec 2022 12:01:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669924908; cv=none; d=google.com; s=arc-20160816; b=sWo2xIQhkix+CJj/JKuMBHbRL89O2hHasfEBKl9ExF1ZGEh0qfesK22HVcj1MFcb0+ PQVyfqroi38YHw5CWiK5x1nXsCqYTWRpWgTiDWt4YewErwl59MZWOYzDkA4ol/eJjRfP EEzAy5TmVnl0WaVpWLWk9S9OEeGoLlvqWdBg4Pb/qiGDeeAmo5KjXJlRMuTTbIQb2mtH S1SluwJ0CRDNnGYPTlWIMutNfCox8NbrOTqwlPn/INxNyibSJ5JstvUYNwn2lHXKwWRt tnSYP8rmvd7W+ks2VdNDhOn9JY4rTh2aQVLCrGYYdoJ9hhJp1xT8J+mYjPlO9IrGl6F6 OJig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RnctwFO59RDhjMAW0dXmnNFb39uXxC4XxPi4Cp1f8js=; b=aNBLRe3565U2Ilv/JlpNMyU3I/OUmg8BLFHjETMul9ScwAgZtfau+5kFUT4EScllzy fwB2ICyd3ZHDoJNEXR0QRTNh5pEc73+0yed13Mtm+Fv2DxylVM1zAFLZdFk8H/S4WsxG i7Vh7ocaMty/hJP7GyWRrQ8u7c9JVeZjB8HNv/Lw+H61SDr+8ogFEf3+8Rolc6Apm9OG Ltw6moPSbTa1Tl1qN3uS/3YO4sphTzkvxbSdiKg9oAuSFZPt0x90qySPbkjwm//4wFmF z5HYpTvbw786HqKQzgmkbZDWipg7MyCuKdjIOO5tffb+CPbAEjosLq4CrR4Vnh8vAboo 1lNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=OWANBxHg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y5-20020a50eb85000000b00467960d3013si4389937edr.43.2022.12.01.12.01.25; Thu, 01 Dec 2022 12:01:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=OWANBxHg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231186AbiLAT5g (ORCPT + 99 others); Thu, 1 Dec 2022 14:57:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230457AbiLAT5T (ORCPT ); Thu, 1 Dec 2022 14:57:19 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D65FFBA602 for ; Thu, 1 Dec 2022 11:57:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669924638; x=1701460638; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I7uBgAnaB7CJhvzOf++h2sYTBFzxqutPFL074As47JI=; b=OWANBxHgxBh+/zMe8oobzcekc60aUCvJ8RGjDRLAxswhpCaKawLmZn/R v+cd5MkOZmn6NWZuOhOC6ZqMTLnFOFwlJqLDUCCKTWjvMSJ7VxwDrPYPg rLGGIUT1dka+FMZ28gdwqkIWXrfRPYaRpL4vMIfQNC1DqZVSirg7+Xdgf 7kzqXwQbz8q5KjigMqDmxrMxjWl1RkZkLHCY6LI1NncYWQLBPVjBwReWR YA+vl8clSi0VDitvss2KRSpZAtM6ZtROzBHKWjMXJBrhRWgRjJZMGRpHH lPPWD4YWG3/uj4hyciFe0ca6dQd5efdzbanA8GcNkU7zoaPj0U0VsYIF3 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="303391877" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="303391877" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 11:57:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708205109" X-IronPort-AV: E=Sophos;i="5.96,210,1665471600"; d="scan'208";a="708205109" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2022 11:57:17 -0800 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: ak@linux.intel.com, eranian@google.com, irogers@google.com, Kan Liang Subject: [PATCH 5/9] perf/x86/intel: Support Architectural PerfMon Extension leaf Date: Thu, 1 Dec 2022 11:57:00 -0800 Message-Id: <20221201195704.2330866-5-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221201195704.2330866-1-kan.liang@linux.intel.com> References: <20221201195704.2330866-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751043181362821671?= X-GMAIL-MSGID: =?utf-8?q?1751043181362821671?= From: Kan Liang The new CPUID leaf 0x23 reports the "true view" of PMU resources. The sub-leaf 1 reports the available general-purpose counters and fixed counters. Update the number of counters and fixed counters when the sub-leaf is detected. Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 22 ++++++++++++++++++++++ arch/x86/include/asm/perf_event.h | 8 ++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index b97eb3bff6ae..9d49c6db40d3 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4588,6 +4588,25 @@ static void flip_smm_bit(void *data) } } +static void intel_pmu_check_num_counters(int *num_counters, + int *num_counters_fixed, + u64 *intel_ctrl, u64 fixed_mask); + +static void update_pmu_cap(struct x86_hybrid_pmu *pmu) +{ + unsigned int sub_bitmaps = cpuid_eax(ARCH_PERFMON_EXT_LEAF); + unsigned int eax, ebx, ecx, edx; + + if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) { + cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, + &eax, &ebx, &ecx, &edx); + pmu->num_counters = fls(eax); + pmu->num_counters_fixed = fls(ebx); + intel_pmu_check_num_counters(&pmu->num_counters, &pmu->num_counters_fixed, + &pmu->intel_ctrl, ebx); + } +} + static bool init_hybrid_pmu(int cpu) { struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); @@ -4613,6 +4632,9 @@ static bool init_hybrid_pmu(int cpu) if (!cpumask_empty(&pmu->supported_cpus)) goto end; + if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) + update_pmu_cap(pmu); + if (!check_hw_exists(&pmu->pmu, pmu->num_counters, pmu->num_counters_fixed)) return false; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 9ac46dbe57d4..98efe1d4005b 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -159,6 +159,14 @@ union cpuid10_edx { unsigned int full; }; +/* + * Intel "Architectural Performance Monitoring extension" CPUID + * detection/enumeration details: + */ +#define ARCH_PERFMON_EXT_LEAF 0x00000023 +#define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT 0x1 +#define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1 + /* * Intel Architectural LBR CPUID detection/enumeration details: */