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[2620:137:e000::1:20]) by mx.google.com with ESMTP id gz16-20020a170907a05000b007882936243fsi2196481ejc.772.2022.11.30.20.53.18; Wed, 30 Nov 2022 20:53:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Hv8iJC8D; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229702AbiLAEwJ (ORCPT + 99 others); Wed, 30 Nov 2022 23:52:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229800AbiLAEvw (ORCPT ); Wed, 30 Nov 2022 23:51:52 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 317359FEE3; Wed, 30 Nov 2022 20:51:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669870302; x=1701406302; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nNVIJLQfTjWu3kqIfeza4XQ0npUMnntm2O5yi398Ywk=; b=Hv8iJC8Dq5aqS6NOg9rzgaD9coA8ZYJircx69XMMb2mp8ElQvUxAWwYj yTX933au5U8QXnnIZswa6jtztE1iiY0RQDVIsR55hMVZaqxbLKhDHkRpg i2OB8R4b+lV87odbaWEuJK6/CyyGrClS3CsLvKDBvSNC0Ipn/Br8OYaEy 6OMYROkZgBFVKW1jSc3XbKaZ5iDmblDh7BzEOzWTQad7YKMIPBGUlToDn J7Y/l40nZQm33+bzqWCDMIG/0a1909TFlgjrQlJ5YWIYMx5DzLbLg84wI 0K3CoRqsK839BrLcAuAwKla+iM5IvRkd+mXdo93/lu9ThL7JHJxUvXMjQ w==; X-IronPort-AV: E=Sophos;i="5.96,207,1665471600"; d="scan'208";a="185988802" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Nov 2022 21:51:41 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 30 Nov 2022 21:51:37 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 30 Nov 2022 21:51:30 -0700 From: Kumaravel Thiagarajan To: , CC: , , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v6 tty-next 4/4] serial: 8250_pci1xxxx: Add power management functions to quad-uart driver Date: Thu, 1 Dec 2022 10:21:46 +0530 Message-ID: <20221201045146.1055913-5-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201045146.1055913-1-kumaravel.thiagarajan@microchip.com> References: <20221201045146.1055913-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750986049563973776?= X-GMAIL-MSGID: =?utf-8?q?1750986049563973776?= pci1xxxx's quad-uart function has the capability to wake up UART from suspend state. Enable wakeup before entering into suspend and disable wakeup on resume. Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan --- Changes in v6: - No Change Changes in v5: - Corrected commit message Changes in v4: - No Change Changes in v3: - Handled race condition in suspend and resume callbacks Changes in v2: - Use DEFINE_SIMPLE_DEV_PM_OPS instead of SIMPLE_DEV_PM_OPS. - Use pm_sleep_ptr instead of CONFIG_PM_SLEEP. - Change the return data type of pci1xxxx_port_suspend to bool from int. --- drivers/tty/serial/8250/8250_pci1xxxx.c | 116 ++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index 7585066d6baf..594f0152daf2 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -192,6 +192,116 @@ static const struct serial_rs485 pci1xxxx_rs485_supported = { /* Delay RTS before send is not supported */ }; +static bool pci1xxxx_port_suspend(int line) +{ + struct uart_8250_port *up = serial8250_get_port(line); + struct uart_port *port = &up->port; + struct tty_port *tport = &port->state->port; + unsigned long flags; + bool ret = false; + u8 wakeup_mask; + + mutex_lock(&tport->mutex); + if (port->suspended == 0 && port->dev) { + wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); + + spin_lock_irqsave(&port->lock, flags); + port->mctrl &= ~TIOCM_OUT2; + port->ops->set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + + ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS; + } + + writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); + mutex_unlock(&tport->mutex); + + return ret; +} + +static void pci1xxxx_port_resume(int line) +{ + struct uart_8250_port *up = serial8250_get_port(line); + struct uart_port *port = &up->port; + struct tty_port *tport = &port->state->port; + unsigned long flags; + + mutex_lock(&tport->mutex); + writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); + writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); + + if (port->suspended == 0) { + spin_lock_irqsave(&port->lock, flags); + port->mctrl |= TIOCM_OUT2; + port->ops->set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + } + mutex_unlock(&tport->mutex); +} + +static int pci1xxxx_suspend(struct device *dev) +{ + struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); + struct pci_dev *pcidev = to_pci_dev(dev); + bool wakeup = false; + unsigned int data; + void __iomem *p; + int i; + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) { + serial8250_suspend_port(priv->line[i]); + wakeup |= pci1xxxx_port_suspend(priv->line[i]); + } + } + + p = pci_ioremap_bar(pcidev, 0); + if (!p) { + dev_err(dev, "remapping of bar 0 memory failed"); + return -ENOMEM; + } + + data = readl(p + UART_RESET_REG); + writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); + + if (wakeup) + writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG); + + iounmap(p); + device_set_wakeup_enable(dev, true); + pci_wake_from_d3(pcidev, true); + + return 0; +} + +static int pci1xxxx_resume(struct device *dev) +{ + struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); + struct pci_dev *pcidev = to_pci_dev(dev); + unsigned int data; + void __iomem *p; + int i; + + p = pci_ioremap_bar(pcidev, 0); + if (!p) { + dev_err(dev, "remapping of bar 0 memory failed"); + return -ENOMEM; + } + + data = readl(p + UART_RESET_REG); + writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); + iounmap(p); + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) { + pci1xxxx_port_resume(priv->line[i]); + serial8250_resume_port(priv->line[i]); + } + } + + return 0; +} + static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, struct uart_8250_port *port, int port_idx) { @@ -323,6 +433,9 @@ static void pci1xxxx_serial_remove(struct pci_dev *dev) } } +static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, + pci1xxxx_resume); + static const struct pci_device_id pci1xxxx_pci_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, @@ -337,6 +450,9 @@ static struct pci_driver pci1xxxx_pci_driver = { .name = "pci1xxxx serial", .probe = pci1xxxx_serial_probe, .remove = pci1xxxx_serial_remove, + .driver = { + .pm = pm_sleep_ptr(&pci1xxxx_pm_ops), + }, .id_table = pci1xxxx_pci_tbl, }; module_pci_driver(pci1xxxx_pci_driver);