Message ID | 20221129144742.2935581-2-conor.dooley@microchip.com |
---|---|
State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 5-20020a630405000000b0046fea9618cdsi15890071pge.323.2022.11.29.06.51.41; Tue, 29 Nov 2022 06:51:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=DA7JrLVp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234926AbiK2OvZ (ORCPT <rfc822;rbbytesnap@gmail.com> + 99 others); Tue, 29 Nov 2022 09:51:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230391AbiK2OvS (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 29 Nov 2022 09:51:18 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D083BAD; Tue, 29 Nov 2022 06:51:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669733477; x=1701269477; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CX12l/BYcHckW0nxt5dW6uGaSf9bcCVSRsIUm2MrbaY=; b=DA7JrLVpepXpqVe7J3e2kwZ+2bgGr0OHLrpTZxiKLMLF79BDOa4stEqY I8B2ZS8uBISd6Z0UqtscpECyUSiJcZAItm+PRAGz7A3DTBy3tf6r4+5ZQ SIxG3jkIfvUBkTTMwlcmtSbM8qqeO66s1Ua5DS2ANj6uuX0TndFDDM49f N8YbB11V68H0m7QlHoOxap31wAWajstPyc+lCepwE7XgJ3/7G2LnRVpyn FSe3tfWz6kaBrc3YHQgGq8SmmK2IqTfFZlHfh1zqnHtxm7S/9qqg9d95W Oacz2NlwhR1DWxiJhHbM5Sqwyeg9D+Hq3ANE0czNXepfLAGNZT053nBqU A==; X-IronPort-AV: E=Sophos;i="5.96,203,1665471600"; d="scan'208";a="190983230" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Nov 2022 07:51:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 29 Nov 2022 07:51:15 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 29 Nov 2022 07:51:13 -0700 From: Conor Dooley <conor.dooley@microchip.com> To: <linux-riscv@lists.infradead.org> CC: Conor Dooley <conor.dooley@microchip.com>, <ajones@ventanamicro.com>, <aou@eecs.berkeley.edu>, <conor@kernel.org>, <devicetree@vger.kernel.org>, <guoren@kernel.org>, <heiko@sntech.de>, <krzysztof.kozlowski+dt@linaro.org>, <linux-kernel@vger.kernel.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <robh+dt@kernel.org> Subject: [RFC 1/2] RISC-V: clarify ISA string ordering rules in cpu.c Date: Tue, 29 Nov 2022 14:47:42 +0000 Message-ID: <20221129144742.2935581-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <Y4XvnHIPw8ZuBZEk@wendy> References: <Y4XvnHIPw8ZuBZEk@wendy> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750842490836613244?= X-GMAIL-MSGID: =?utf-8?q?1750842490836613244?= |
Series |
[RFC,1/2] RISC-V: clarify ISA string ordering rules in cpu.c
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Commit Message
Conor Dooley
Nov. 29, 2022, 2:47 p.m. UTC
While the list of rules may have been accurate when created, it now
lacks some clarity in the face of isa-manual updates. Specifically:
- there is no mention here of a distinction between regular 'Z'
extensions which are "Additional Standard Extensions" and "Zxm"
extensions which are "Standard Machine-Level Extensions"
- there is also no explicit mention of where either should be sorted in
the list
- underscores are only required between two *multi-letter* extensions but
the list of rules implies that this is required between a multi-letter
extension and any other extension. IOW "rv64imafdzicsr_zifencei" is a
valid string
Attempt to clean up the list of rules, by adding information on the
above & sprinkling in some white space for readability.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/kernel/cpu.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
Comments
On Tue, Nov 29, 2022 at 02:47:42PM +0000, Conor Dooley wrote: > While the list of rules may have been accurate when created, it now > lacks some clarity in the face of isa-manual updates. Specifically: > > - there is no mention here of a distinction between regular 'Z' > extensions which are "Additional Standard Extensions" and "Zxm" > extensions which are "Standard Machine-Level Extensions" > > - there is also no explicit mention of where either should be sorted in > the list > > - underscores are only required between two *multi-letter* extensions but > the list of rules implies that this is required between a multi-letter > extension and any other extension. IOW "rv64imafdzicsr_zifencei" is a > valid string > > Attempt to clean up the list of rules, by adding information on the > above & sprinkling in some white space for readability. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/kernel/cpu.c | 22 +++++++++++++++++----- > 1 file changed, 17 insertions(+), 5 deletions(-) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 852ecccd8920..5e42c92a8456 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -120,20 +120,32 @@ device_initcall(riscv_cpuinfo_init); > .uprop = #UPROP, \ > .isa_ext_id = EXTID, \ > } > + > /* > * Here are the ordering rules of extension naming defined by RISC-V > * specification : > - * 1. All extensions should be separated from other multi-letter extensions > - * by an underscore. > + * > + * 1. All multi-letter extensions should be separated from other multi-letter > + * extensions by an underscore. > + * > * 2. The first letter following the 'Z' conventionally indicates the most > * closely related alphabetical extension category, IMAFDQLCBKJTPVH. > - * If multiple 'Z' extensions are named, they should be ordered first > - * by category, then alphabetically within a category. > + * 'Z' extensions should be sorted after single-letter extensions and before > + * any higher-privileged extensions. > + * If multiple 'Z' extensions are named, they should be ordered first by > + * category, then alphabetically within a category. > + * > * 3. Standard supervisor-level extensions (starts with 'S') should be > * listed after standard unprivileged extensions. If multiple > * supervisor-level extensions are listed, they should be ordered > * alphabetically. > - * 4. Non-standard extensions (starts with 'X') must be listed after all > + * > + * 4 Standard machine-level extensions (starts with 'Zxm') should be > + * listed after any lower-privileged, standard extensions. If multiple > + * machine-level extensions are listed, they should be ordered > + * alphabetically. > + * > + * 5. Non-standard extensions (starts with 'X') must be listed after all > * standard extensions. They must be separated from other multi-letter > * extensions by an underscore. > */ > -- > 2.38.1 > Alternatively, we could change the comment to just point out the spec chapter and provide an example, e.g. /* * The canonical order of ISA extension names in the ISA string is defined in * chapter 27 of the unprivileged spec. An example string following the * order is * * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux * * Notice how Z-extensions are first sorted by category using the canonical * order of the first letter following the Z. Extension groups are in the * order specified in chapter 27. Extensions within each group are sorted * alphabetically. */ Thanks, drew
On Tue, Nov 29, 2022 at 05:12:23PM +0100, Andrew Jones wrote: > On Tue, Nov 29, 2022 at 02:47:42PM +0000, Conor Dooley wrote: > > While the list of rules may have been accurate when created, it now > > lacks some clarity in the face of isa-manual updates. Specifically: > > > > - there is no mention here of a distinction between regular 'Z' > > extensions which are "Additional Standard Extensions" and "Zxm" > > extensions which are "Standard Machine-Level Extensions" > > > > - there is also no explicit mention of where either should be sorted in > > the list > > > > - underscores are only required between two *multi-letter* extensions but > > the list of rules implies that this is required between a multi-letter > > extension and any other extension. IOW "rv64imafdzicsr_zifencei" is a > > valid string > > > > Attempt to clean up the list of rules, by adding information on the > > above & sprinkling in some white space for readability. > > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > --- > > arch/riscv/kernel/cpu.c | 22 +++++++++++++++++----- > > 1 file changed, 17 insertions(+), 5 deletions(-) > > > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index 852ecccd8920..5e42c92a8456 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -120,20 +120,32 @@ device_initcall(riscv_cpuinfo_init); > > .uprop = #UPROP, \ > > .isa_ext_id = EXTID, \ > > } > > + > > /* > > * Here are the ordering rules of extension naming defined by RISC-V > > * specification : > > - * 1. All extensions should be separated from other multi-letter extensions > > - * by an underscore. > > + * > > + * 1. All multi-letter extensions should be separated from other multi-letter > > + * extensions by an underscore. > > + * > > * 2. The first letter following the 'Z' conventionally indicates the most > > * closely related alphabetical extension category, IMAFDQLCBKJTPVH. > > - * If multiple 'Z' extensions are named, they should be ordered first > > - * by category, then alphabetically within a category. > > + * 'Z' extensions should be sorted after single-letter extensions and before > > + * any higher-privileged extensions. > > + * If multiple 'Z' extensions are named, they should be ordered first by > > + * category, then alphabetically within a category. > > + * > > * 3. Standard supervisor-level extensions (starts with 'S') should be > > * listed after standard unprivileged extensions. If multiple > > * supervisor-level extensions are listed, they should be ordered > > * alphabetically. > > - * 4. Non-standard extensions (starts with 'X') must be listed after all > > + * > > + * 4 Standard machine-level extensions (starts with 'Zxm') should be > > + * listed after any lower-privileged, standard extensions. If multiple > > + * machine-level extensions are listed, they should be ordered > > + * alphabetically. > > + * > > + * 5. Non-standard extensions (starts with 'X') must be listed after all > > * standard extensions. They must be separated from other multi-letter > > * extensions by an underscore. > > */ > > -- > > 2.38.1 > > > > Alternatively, we could change the comment to just point out the spec > chapter and provide an example, e.g. IDK, maybe add the reference & the example but keep the summary? > /* > * The canonical order of ISA extension names in the ISA string is defined in > * chapter 27 of the unprivileged spec. An example string following the > * order is > * > * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux > * > * Notice how Z-extensions are first sorted by category using the canonical > * order of the first letter following the Z. Extension groups are in the > * order specified in chapter 27. Extensions within each group are sorted > * alphabetically. > */ > > > Thanks, > drew
On Tue, Nov 29, 2022 at 04:54:19PM +0000, Conor Dooley wrote: > On Tue, Nov 29, 2022 at 05:12:23PM +0100, Andrew Jones wrote: > > On Tue, Nov 29, 2022 at 02:47:42PM +0000, Conor Dooley wrote: > > > While the list of rules may have been accurate when created, it now > > > lacks some clarity in the face of isa-manual updates. Specifically: > > > > > > - there is no mention here of a distinction between regular 'Z' > > > extensions which are "Additional Standard Extensions" and "Zxm" > > > extensions which are "Standard Machine-Level Extensions" > > > > > > - there is also no explicit mention of where either should be sorted in > > > the list > > > > > > - underscores are only required between two *multi-letter* extensions but > > > the list of rules implies that this is required between a multi-letter > > > extension and any other extension. IOW "rv64imafdzicsr_zifencei" is a > > > valid string > > > > > > Attempt to clean up the list of rules, by adding information on the > > > above & sprinkling in some white space for readability. > > > > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > > --- > > > arch/riscv/kernel/cpu.c | 22 +++++++++++++++++----- > > > 1 file changed, 17 insertions(+), 5 deletions(-) > > > > > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > > index 852ecccd8920..5e42c92a8456 100644 > > > --- a/arch/riscv/kernel/cpu.c > > > +++ b/arch/riscv/kernel/cpu.c > > > @@ -120,20 +120,32 @@ device_initcall(riscv_cpuinfo_init); > > > .uprop = #UPROP, \ > > > .isa_ext_id = EXTID, \ > > > } > > > + > > > /* > > > * Here are the ordering rules of extension naming defined by RISC-V > > > * specification : > > > - * 1. All extensions should be separated from other multi-letter extensions > > > - * by an underscore. > > > + * > > > + * 1. All multi-letter extensions should be separated from other multi-letter > > > + * extensions by an underscore. > > > + * > > > * 2. The first letter following the 'Z' conventionally indicates the most > > > * closely related alphabetical extension category, IMAFDQLCBKJTPVH. > > > - * If multiple 'Z' extensions are named, they should be ordered first > > > - * by category, then alphabetically within a category. > > > + * 'Z' extensions should be sorted after single-letter extensions and before > > > + * any higher-privileged extensions. > > > + * If multiple 'Z' extensions are named, they should be ordered first by > > > + * category, then alphabetically within a category. > > > + * > > > * 3. Standard supervisor-level extensions (starts with 'S') should be > > > * listed after standard unprivileged extensions. If multiple > > > * supervisor-level extensions are listed, they should be ordered > > > * alphabetically. > > > - * 4. Non-standard extensions (starts with 'X') must be listed after all > > > + * > > > + * 4 Standard machine-level extensions (starts with 'Zxm') should be > > > + * listed after any lower-privileged, standard extensions. If multiple > > > + * machine-level extensions are listed, they should be ordered > > > + * alphabetically. > > > + * > > > + * 5. Non-standard extensions (starts with 'X') must be listed after all > > > * standard extensions. They must be separated from other multi-letter > > > * extensions by an underscore. > > > */ > > > -- > > > 2.38.1 > > > > > > > Alternatively, we could change the comment to just point out the spec > > chapter and provide an example, e.g. > > IDK, maybe add the reference & the example but keep the summary? It risks needing to synchronize the comment with the spec. Also, the comment doesn't need to reproduce the flexible specifications, since Linux has a single implementation (it always puts an underscore between single-letter extensions and the first multi-letter extension, for example). So, rather than paraphrase too much of the spec, we could just point out Linux's specific implementation (with the help of an example). I don't feel that strongly about it though, so we can keep the text the spec paraphrasing too. Thanks, drew > > > /* > > * The canonical order of ISA extension names in the ISA string is defined in > > * chapter 27 of the unprivileged spec. An example string following the > > * order is > > * > > * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux > > * > > * Notice how Z-extensions are first sorted by category using the canonical > > * order of the first letter following the Z. Extension groups are in the > > * order specified in chapter 27. Extensions within each group are sorted > > * alphabetically. > > */ > > > > > > Thanks, > > drew
On Tue, Nov 29, 2022 at 06:19:51PM +0100, Andrew Jones wrote: > On Tue, Nov 29, 2022 at 04:54:19PM +0000, Conor Dooley wrote: > > On Tue, Nov 29, 2022 at 05:12:23PM +0100, Andrew Jones wrote: > > > On Tue, Nov 29, 2022 at 02:47:42PM +0000, Conor Dooley wrote: > > > > While the list of rules may have been accurate when created, it now > > > > lacks some clarity in the face of isa-manual updates. Specifically: > > > > > > > > - there is no mention here of a distinction between regular 'Z' > > > > extensions which are "Additional Standard Extensions" and "Zxm" > > > > extensions which are "Standard Machine-Level Extensions" > > > > > > > > - there is also no explicit mention of where either should be sorted in > > > > the list > > > > > > > > - underscores are only required between two *multi-letter* extensions but > > > > the list of rules implies that this is required between a multi-letter > > > > extension and any other extension. IOW "rv64imafdzicsr_zifencei" is a > > > > valid string > > > > > > > > Attempt to clean up the list of rules, by adding information on the > > > > above & sprinkling in some white space for readability. > > > > > > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > > > --- > > > > arch/riscv/kernel/cpu.c | 22 +++++++++++++++++----- > > > > 1 file changed, 17 insertions(+), 5 deletions(-) > > > > > > > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > > > index 852ecccd8920..5e42c92a8456 100644 > > > > --- a/arch/riscv/kernel/cpu.c > > > > +++ b/arch/riscv/kernel/cpu.c > > > > @@ -120,20 +120,32 @@ device_initcall(riscv_cpuinfo_init); > > > > .uprop = #UPROP, \ > > > > .isa_ext_id = EXTID, \ > > > > } > > > > + > > > > /* > > > > * Here are the ordering rules of extension naming defined by RISC-V > > > > * specification : > > > > - * 1. All extensions should be separated from other multi-letter extensions > > > > - * by an underscore. > > > > + * > > > > + * 1. All multi-letter extensions should be separated from other multi-letter > > > > + * extensions by an underscore. > > > > + * > > > > * 2. The first letter following the 'Z' conventionally indicates the most > > > > * closely related alphabetical extension category, IMAFDQLCBKJTPVH. > > > > - * If multiple 'Z' extensions are named, they should be ordered first > > > > - * by category, then alphabetically within a category. > > > > + * 'Z' extensions should be sorted after single-letter extensions and before > > > > + * any higher-privileged extensions. > > > > + * If multiple 'Z' extensions are named, they should be ordered first by > > > > + * category, then alphabetically within a category. > > > > + * > > > > * 3. Standard supervisor-level extensions (starts with 'S') should be > > > > * listed after standard unprivileged extensions. If multiple > > > > * supervisor-level extensions are listed, they should be ordered > > > > * alphabetically. > > > > - * 4. Non-standard extensions (starts with 'X') must be listed after all > > > > + * > > > > + * 4 Standard machine-level extensions (starts with 'Zxm') should be > > > > + * listed after any lower-privileged, standard extensions. If multiple > > > > + * machine-level extensions are listed, they should be ordered > > > > + * alphabetically. > > > > + * > > > > + * 5. Non-standard extensions (starts with 'X') must be listed after all > > > > * standard extensions. They must be separated from other multi-letter > > > > * extensions by an underscore. > > > > */ > > > > -- > > > > 2.38.1 > > > > > > > > > > Alternatively, we could change the comment to just point out the spec > > > chapter and provide an example, e.g. > > > > IDK, maybe add the reference & the example but keep the summary? > > It risks needing to synchronize the comment with the spec. Heh, see I almost see this as an *advantage* of this approach! > Also, the > comment doesn't need to reproduce the flexible specifications, since > Linux has a single implementation (it always puts an underscore between > single-letter extensions and the first multi-letter extension, for > example). So, rather than paraphrase too much of the spec, we could just > point out Linux's specific implementation (with the help of an example). You're right here though. I've had my head stuck in the incoming-string side of things rather than outgoing. I'll wait for the all clear from Above, but ideally I'll reword this explaining where this info shows up (and therefore why it needs to be ordered), what elements of the rules matter here (entirely ordering) and then include your bits from below? > I don't feel that strongly about it though, so we can keep the text > the spec paraphrasing too. > > > /* > > > * The canonical order of ISA extension names in the ISA string is defined in > > > * chapter 27 of the unprivileged spec. An example string following the > > > * order is > > > * > > > * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux > > > * > > > * Notice how Z-extensions are first sorted by category using the canonical > > > * order of the first letter following the Z. Extension groups are in the > > > * order specified in chapter 27. Extensions within each group are sorted > > > * alphabetically. > > > */
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 852ecccd8920..5e42c92a8456 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -120,20 +120,32 @@ device_initcall(riscv_cpuinfo_init); .uprop = #UPROP, \ .isa_ext_id = EXTID, \ } + /* * Here are the ordering rules of extension naming defined by RISC-V * specification : - * 1. All extensions should be separated from other multi-letter extensions - * by an underscore. + * + * 1. All multi-letter extensions should be separated from other multi-letter + * extensions by an underscore. + * * 2. The first letter following the 'Z' conventionally indicates the most * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they should be ordered first - * by category, then alphabetically within a category. + * 'Z' extensions should be sorted after single-letter extensions and before + * any higher-privileged extensions. + * If multiple 'Z' extensions are named, they should be ordered first by + * category, then alphabetically within a category. + * * 3. Standard supervisor-level extensions (starts with 'S') should be * listed after standard unprivileged extensions. If multiple * supervisor-level extensions are listed, they should be ordered * alphabetically. - * 4. Non-standard extensions (starts with 'X') must be listed after all + * + * 4 Standard machine-level extensions (starts with 'Zxm') should be + * listed after any lower-privileged, standard extensions. If multiple + * machine-level extensions are listed, they should be ordered + * alphabetically. + * + * 5. Non-standard extensions (starts with 'X') must be listed after all * standard extensions. They must be separated from other multi-letter * extensions by an underscore. */