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(d-75-76-18-234.oh.cpe.breezeline.net. [75.76.18.234]) by smtp.gmail.com with ESMTPSA id r9-20020a05622a034900b003a526675c07sm7322712qtw.52.2022.11.28.09.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 09:25:02 -0800 (PST) From: Nathan Barrett-Morrison Cc: nathan.morrison@timesys.com, greg.malysa@timesys.com, Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org (open list:SPI NOR SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Subject: [PATCH] mtd: spi-nor: issi: Add in support for IS25LX256 chip, operating in 1S-1S-8S mode. Date: Mon, 28 Nov 2022 12:24:54 -0500 Message-Id: <20221128172455.159787-1-nathan.morrison@timesys.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750762393137609606?= X-GMAIL-MSGID: =?utf-8?q?1750762393137609606?= Adds the is25lx256 entry to the nor_parts table along with the additional fixup logic to operate in 1S-1S-8S mode while programming. Signed-off-by: Nathan Barrett-Morrison --- drivers/mtd/spi-nor/issi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 89a66a19d754..e9b32b726bf3 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -29,6 +29,21 @@ static const struct spi_nor_fixups is25lp256_fixups = { .post_bfpt = is25lp256_post_bfpt_fixups, }; +static void is25lx256_post_sfdp_fixup(struct spi_nor *nor) +{ + /* Fixup page program command to 1S-1S-8S */ + nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_8; + spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_1_8], + SPINOR_OP_PP_1_1_8, SNOR_PROTO_1_1_8); + + /* Disable quad_enable */ + nor->params->quad_enable = NULL; +} + +static struct spi_nor_fixups is25lx256_fixups = { + .post_sfdp = is25lx256_post_sfdp_fixup, +}; + static void pm25lv_nor_late_init(struct spi_nor *nor) { struct spi_nor_erase_map *map = &nor->params->erase_map; @@ -74,6 +89,10 @@ static const struct flash_info issi_nor_parts[] = { NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) .fixups = &is25lp256_fixups }, + { "is25lx256", INFO(0x9d5a19, 0, 128 * 1024, 256) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_READ) + FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + .fixups = &is25lx256_fixups }, /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2)