diff mbox series

arm64: dts: qcom: sm6115: Add geni debug uart node for qup0

Message ID 20221128171215.1768745-1-bhupesh.sharma@linaro.org
State New
Headers
Series arm64: dts: qcom: sm6115: Add geni debug uart node for qup0 |

Commit Message

Bhupesh Sharma Nov. 28, 2022, 5:12 p.m. UTC 
  qup0 on sm6115 / sm4250 has 6 SEs, with SE4 as debug uart.
Add the debug uart node in sm6115 dtsi file.

Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
- Based on linux-next.

 arch/arm64/boot/dts/qcom/sm6115.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Konrad Dybcio Nov. 29, 2022, 1:30 p.m. UTC | #1 
On 28.11.2022 18:12, Bhupesh Sharma wrote:
> qup0 on sm6115 / sm4250 has 6 SEs, with SE4 as debug uart.
> Add the debug uart node in sm6115 dtsi file.
> 
> Cc: Bjorn Andersson <andersson@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
> - Based on linux-next.
> 
>  arch/arm64/boot/dts/qcom/sm6115.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index 0340ed21be05..e4a2440ce544 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -649,6 +649,26 @@ ufs_mem_phy_lanes: phy@4807400 {
>  			};
>  		};
>  
> +		qupv3_id_0: geniqup@4ac0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x4ac0000 0x2000>;
Please pad address to 8 hex digits, same below.

Konrad
> +			clock-names = "m-ahb", "s-ahb";
> +			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			uart4: serial@4a90000 {
> +				compatible = "qcom,geni-debug-uart";
> +				reg = <0x4a90000 0x4000>;
> +				clock-names = "se";
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> +				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +		};
> +
>  		usb_1: usb@4ef8800 {
>  			compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
>  			reg = <0x04ef8800 0x400>;
Bhupesh Sharma Nov. 29, 2022, 6:54 p.m. UTC | #2 
On Tue, 29 Nov 2022 at 19:00, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
>
>
> On 28.11.2022 18:12, Bhupesh Sharma wrote:
> > qup0 on sm6115 / sm4250 has 6 SEs, with SE4 as debug uart.
> > Add the debug uart node in sm6115 dtsi file.
> >
> > Cc: Bjorn Andersson <andersson@kernel.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > - Based on linux-next.
> >
> >  arch/arm64/boot/dts/qcom/sm6115.dtsi | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> > index 0340ed21be05..e4a2440ce544 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> > @@ -649,6 +649,26 @@ ufs_mem_phy_lanes: phy@4807400 {
> >                       };
> >               };
> >
> > +             qupv3_id_0: geniqup@4ac0000 {
> > +                     compatible = "qcom,geni-se-qup";
> > +                     reg = <0x4ac0000 0x2000>;
> Please pad address to 8 hex digits, same below.

Sure, I will fix it in v2.

Thanks,
Bhupesh

> > +                     clock-names = "m-ahb", "s-ahb";
> > +                     clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> > +                              <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> > +                     #address-cells = <1>;
> > +                     #size-cells = <1>;
> > +                     ranges;
> > +
> > +                     uart4: serial@4a90000 {
> > +                             compatible = "qcom,geni-debug-uart";
> > +                             reg = <0x4a90000 0x4000>;
> > +                             clock-names = "se";
> > +                             clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> > +                             interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> > +                             status = "disabled";
> > +                     };
> > +             };
> > +
> >               usb_1: usb@4ef8800 {
> >                       compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
> >                       reg = <0x04ef8800 0x400>;
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 0340ed21be05..e4a2440ce544 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -649,6 +649,26 @@  ufs_mem_phy_lanes: phy@4807400 {
 			};
 		};
 
+		qupv3_id_0: geniqup@4ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x4ac0000 0x2000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			uart4: serial@4a90000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x4a90000 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
 		usb_1: usb@4ef8800 {
 			compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
 			reg = <0x04ef8800 0x400>;