[v5,1/5] x86/cpufeature: add the cpu feature bit for LKGS
Commit Message
From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
Add the CPU feature bit for LKGS (Load "Kernel" GS).
LKGS instruction is introduced with Intel FRED (flexible return and
event delivery) specificaton
https://cdrdv2.intel.com/v1/dl/getContent/678938.
LKGS behaves like the MOV to GS instruction except that it loads
the base address into the IA32_KERNEL_GS_BASE MSR instead of the
GS segment’s descriptor cache, which is exactly what Linux kernel
does to load a user level GS base. Thus, with LKGS, there is no
need to SWAPGS away from the kernel GS base.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
---
Change since V2:
* add "" not to show "lkgs" in /proc/cpuinfo (Chang S. Bae).
---
arch/x86/include/asm/cpufeatures.h | 1 +
tools/arch/x86/include/asm/cpufeatures.h | 1 +
2 files changed, 2 insertions(+)
Comments
On Mon, Nov 28, 2022 at 08:40:24AM -0800, Xin Li wrote:
> From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
>
> Add the CPU feature bit for LKGS (Load "Kernel" GS).
>
> LKGS instruction is introduced with Intel FRED (flexible return and
> event delivery) specificaton
Unknown word [specificaton] in commit message.
Suggestions: ['specification',
Please use a spellchecker for your commit messages.
> https://cdrdv2.intel.com/v1/dl/getContent/678938.
This URL is most likely going to be unstable.
Write instead
"Search for the latest spec in most search engines by doing:
site:intel.com FRED (flexible return and event delivery) specification"
Google etc has indexed it already so it should always pull out the newest
revision.
$ test-apply.sh /tmp/01-x86-cpufeature-add_the_cpu_feature_bit_for_lkgs-new.patch
checking file arch/x86/include/asm/cpufeatures.h
Hunk #1 FAILED at 311.
1 out of 1 hunk FAILED
checking file tools/arch/x86/include/asm/cpufeatures.h
Hunk #1 FAILED at 308.
1 out of 1 hunk FAILED
Apply? (y/n)
I guess you'd need to refresh the patchset against latest tip/master.
Thx.
> > Add the CPU feature bit for LKGS (Load "Kernel" GS).
> >
> > LKGS instruction is introduced with Intel FRED (flexible return and
> > event delivery) specificaton
>
> Unknown word [specificaton] in commit message.
> Suggestions: ['specification',
>
> Please use a spellchecker for your commit messages.
>
> > https://cdrdv2.intel.com/v1/dl/getContent/678938.
>
> This URL is most likely going to be unstable.
>
> Write instead
>
> "Search for the latest spec in most search engines by doing:
>
> site:intel.com FRED (flexible return and event delivery) specification"
Thanks for the suggestion.
> Google etc has indexed it already so it should always pull out the newest revision.
>
> $ test-apply.sh /tmp/01-x86-cpufeature-add_the_cpu_feature_bit_for_lkgs-
> new.patch
> checking file arch/x86/include/asm/cpufeatures.h
> Hunk #1 FAILED at 311.
> 1 out of 1 hunk FAILED
> checking file tools/arch/x86/include/asm/cpufeatures.h
> Hunk #1 FAILED at 308.
> 1 out of 1 hunk FAILED
> Apply? (y/n)
>
> I guess you'd need to refresh the patchset against latest tip/master.
Will rebase on top of latest master and send v6 of the patch set.
Xin
> Thx.
>
> --
> Regards/Gruss,
> Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette
@@ -311,6 +311,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
+#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
@@ -308,6 +308,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
+#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */