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[46.135.44.69]) by smtp.gmail.com with ESMTPSA id v11-20020a5d4b0b000000b002368f6b56desm4207406wrq.18.2022.11.25.03.19.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:19:41 -0800 (PST) Sender: Tomeu Vizoso From: Tomeu Vizoso Cc: Tomeu Vizoso , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/6] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Date: Fri, 25 Nov 2022 12:19:16 +0100 Message-Id: <20221125111921.37261-4-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221125111921.37261-1-tomeu.vizoso@collabora.com> References: <20221125111921.37261-1-tomeu.vizoso@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750467107121507905?= X-GMAIL-MSGID: =?utf-8?q?1750467107121507905?= Based on power initialization sequence in downstream driver. Signed-off-by: Tomeu Vizoso Reviewed-by: Neil Armstrong --- drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c index dd5f2a13ceb5..925cfaf50d11 100644 --- a/drivers/soc/amlogic/meson-ee-pwrc.c +++ b/drivers/soc/amlogic/meson-ee-pwrc.c @@ -46,6 +46,9 @@ #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2) #define HHI_VPU_MEM_PD_REG2 (0x4d << 2) +#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2) +#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2) + struct meson_ee_pwrc; struct meson_ee_pwrc_domain; @@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17); static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18); static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19); +static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { \ + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \ + .sleep_mask = BIT(16) | BIT(17), \ + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \ + .iso_mask = BIT(16) | BIT(17), \ + }; + /* Memory PD Domains */ #define VPU_MEMPD(__reg) \ @@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) }, }; +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = { + { G12A_HHI_NANOQ_MEM_PD_REG0, 0xffffffff }, + { G12A_HHI_NANOQ_MEM_PD_REG1, 0xffffffff }, +}; + #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ { \ .name = __name, \ @@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, pwrc_ee_is_powered_off, 11, 2), [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), + [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna, + pwrc_ee_is_powered_off), }; static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {