Message ID | 20221125040604.5051-12-weijiang.yang@intel.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3797331wrr; Thu, 24 Nov 2022 22:12:23 -0800 (PST) X-Google-Smtp-Source: AA0mqf7sZFQoF0kXAFK6VDGHH6kRI1FKT6Pf8uobCHaWonuE+Xly1OtHN02FR/HC7nP3CoggQKZc X-Received: by 2002:aa7:8054:0:b0:56c:4303:a93d with SMTP id y20-20020aa78054000000b0056c4303a93dmr21288399pfm.73.1669356743540; Thu, 24 Nov 2022 22:12:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669356743; cv=none; d=google.com; s=arc-20160816; b=oZ0GwbLe0H4vpnY6ot0sfPS4gvaeR3kn6WApdJu+SftsoQhBT0WmdAGg7P4FyjsLzK n3c90gntfnfgAk39M9CeOPU2jPZjj6J3+dh5uQ40n9unewvuGkewVUy279IKPDCx8dXq SR0LpO0/K5anZxxpdH/O71yHP183aGwMd2BBFhneEV0ODCwKmh8e7nZIcnO5+iAb6Ihi X025fwTvPviA4wDAqq9TI7eusujfT/+ayH2NwD9sWqS/pymo1nsuJPzdTIVAJ2PaJ1Qo dcrf8osRrp1Khw+QoBKAC6MUaTbZkOiGpHGKGNcKtLsVeEmkjEdhxdFspjhQWNzwjxFc XS0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lxzZG9AxB7xmlHUKkHpPNVBHnondu8QFtzvOEx7jSp4=; b=nQPMHR2UE/t32HdsxdM6vE5i+GvWTYgyUjICJ/QNeltQW0wniVXXtWThZE0MA9Bbta xFalb7G/5Z1lnjLhOnljUyXeD827/8Frw0vSG1VjS02qV6a3r1G61C0+gYILmVUXIBc+ 81WzAFRcPibYGI8gD1pfBRqsb0fD9ompmHu1IEkUFzXiuME3iKkmRL86bzBu3k6pi2bW 0AvV/Phibqnn+8yjPKVroYJKU02bo1tYk0Uzsxggw6GcT3jNx7cY51ODHEYLUiXrXvix 2hZ7P8XU9AnHCEozDQeE/8NymO62BW/cynOzt78LKqqEavJMdm+DPlfjXUIYg1ZI/eDk W+Cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=U5D3pNhX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n18-20020a170902d2d200b0017145b821d2si3237583plc.477.2022.11.24.22.12.10; Thu, 24 Nov 2022 22:12:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=U5D3pNhX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229840AbiKYGKt (ORCPT <rfc822;zxc52fgh@gmail.com> + 99 others); Fri, 25 Nov 2022 01:10:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229753AbiKYGKU (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Fri, 25 Nov 2022 01:10:20 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E622F22BD6; Thu, 24 Nov 2022 22:10:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669356613; x=1700892613; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4eg8NP/fJsLd5N9GLFwt3wbkem8wIETGsx0i+IB7Xnc=; b=U5D3pNhX4mHG06hyTw0MmsWE8R++7J3xpnujZ+Z+7EzCmpAsRHfyqqns LxprgLE7xrGjBVNljPL5jejIfyJOYiaM5QQ1Ff05Uc0ccNgQsC9ZYwgY4 0YoTTUlL+CZDY8WmlGzWgKzI0w0qyYSc5lOqPdm4w//KSouQAKm6DBl2l TIDlIVYd9ASVyhpAK0nrGkHqGAVaW4Vk7UQf4wYwwDAi6dVIXXjMdaOkR WiVRb266ZlXXnT2tEssGBFSRP5zi/WzYpUwX0WpUy7yqYQJP3EfCRXNlI k2Ev5EysFVmEq74Y5vEmaVq4MKpa18cXogJGmYbgLe9lz0bpWLnj61HlA g==; X-IronPort-AV: E=McAfee;i="6500,9779,10541"; a="313116831" X-IronPort-AV: E=Sophos;i="5.96,192,1665471600"; d="scan'208";a="313116831" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Nov 2022 22:10:08 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10541"; a="784838500" X-IronPort-AV: E=Sophos;i="5.96,192,1665471600"; d="scan'208";a="784838500" Received: from embargo.jf.intel.com ([10.165.9.183]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Nov 2022 22:10:07 -0800 From: Yang Weijiang <weijiang.yang@intel.com> To: seanjc@google.com, pbonzini@redhat.com, jmattson@google.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: like.xu.linux@gmail.com, kan.liang@linux.intel.com, wei.w.wang@intel.com, weijiang.yang@intel.com, Like Xu <like.xu@linux.intel.com> Subject: [PATCH v2 11/15] KVM: x86: Add XSAVE Support for Architectural LBR Date: Thu, 24 Nov 2022 23:06:00 -0500 Message-Id: <20221125040604.5051-12-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221125040604.5051-1-weijiang.yang@intel.com> References: <20221125040604.5051-1-weijiang.yang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750447416722057282?= X-GMAIL-MSGID: =?utf-8?q?1750447416722057282?= |
Series |
Introduce Architectural LBR for vPMU
|
|
Commit Message
Yang, Weijiang
Nov. 25, 2022, 4:06 a.m. UTC
From: Like Xu <like.xu@linux.intel.com> On processors supporting XSAVES and XRSTORS, Architectural LBR XSAVE support is enumerated from CPUID.(EAX=0DH, ECX=1):ECX[bit 15]. The detailed sub-leaf for Arch LBR is enumerated in CPUID.(0DH, 0FH). XSAVES provides a faster means than RDMSR for guest to read all LBRs. When guest IA32_XSS[bit 15] is set, the Arch LBR state can be saved using XSAVES and restored by XRSTORS with the appropriate RFBM. Signed-off-by: Like Xu <like.xu@linux.intel.com> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> --- arch/x86/kvm/vmx/vmx.c | 4 ++++ arch/x86/kvm/x86.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-)
Comments
On Thu, Nov 24, 2022, Yang Weijiang wrote: > From: Like Xu <like.xu@linux.intel.com> > > On processors supporting XSAVES and XRSTORS, Architectural LBR XSAVE > support is enumerated from CPUID.(EAX=0DH, ECX=1):ECX[bit 15]. > The detailed sub-leaf for Arch LBR is enumerated in CPUID.(0DH, 0FH). > > XSAVES provides a faster means than RDMSR for guest to read all LBRs. > When guest IA32_XSS[bit 15] is set, the Arch LBR state can be saved using > XSAVES and restored by XRSTORS with the appropriate RFBM. > > Signed-off-by: Like Xu <like.xu@linux.intel.com> > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > --- > arch/x86/kvm/vmx/vmx.c | 4 ++++ > arch/x86/kvm/x86.c | 2 +- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c > index 359da38a19a1..3bc892e8cf7a 100644 > --- a/arch/x86/kvm/vmx/vmx.c > +++ b/arch/x86/kvm/vmx/vmx.c > @@ -7733,6 +7733,10 @@ static __init void vmx_set_cpu_caps(void) > kvm_cpu_cap_check_and_set(X86_FEATURE_DS); > kvm_cpu_cap_check_and_set(X86_FEATURE_DTES64); > } > + if (!cpu_has_vmx_arch_lbr()) { > + kvm_cpu_cap_clear(X86_FEATURE_ARCH_LBR); No, this needs to be opt-in, not opt-out. I.e. omit the flag from common CPUID code and set it if and only if it's fully supported. It's not out of the realm of possibilities that AMD might want to support arch LBRs, at which point those CPUs would explode. > + kvm_caps.supported_xss &= ~XFEATURE_MASK_LBR; > + } > > if (!enable_pmu) > kvm_cpu_cap_clear(X86_FEATURE_PDCM); > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 889be0c9176d..38df08d9d0cb 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -217,7 +217,7 @@ static struct kvm_user_return_msrs __percpu *user_return_msrs; > | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ > | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) > > -#define KVM_SUPPORTED_XSS 0 > +#define KVM_SUPPORTED_XSS XFEATURE_MASK_LBR > > u64 __read_mostly host_efer; > EXPORT_SYMBOL_GPL(host_efer); > -- > 2.27.0 >
On 1/28/2023 6:07 AM, Sean Christopherson wrote: > On Thu, Nov 24, 2022, Yang Weijiang wrote: >> From: Like Xu <like.xu@linux.intel.com> >> >> On processors supporting XSAVES and XRSTORS, Architectural LBR XSAVE >> support is enumerated from CPUID.(EAX=0DH, ECX=1):ECX[bit 15]. >> The detailed sub-leaf for Arch LBR is enumerated in CPUID.(0DH, 0FH). >> >> XSAVES provides a faster means than RDMSR for guest to read all LBRs. >> When guest IA32_XSS[bit 15] is set, the Arch LBR state can be saved using >> XSAVES and restored by XRSTORS with the appropriate RFBM. >> >> Signed-off-by: Like Xu <like.xu@linux.intel.com> >> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> >> --- >> arch/x86/kvm/vmx/vmx.c | 4 ++++ >> arch/x86/kvm/x86.c | 2 +- >> 2 files changed, 5 insertions(+), 1 deletion(-) >> >> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c >> index 359da38a19a1..3bc892e8cf7a 100644 >> --- a/arch/x86/kvm/vmx/vmx.c >> +++ b/arch/x86/kvm/vmx/vmx.c >> @@ -7733,6 +7733,10 @@ static __init void vmx_set_cpu_caps(void) >> kvm_cpu_cap_check_and_set(X86_FEATURE_DS); >> kvm_cpu_cap_check_and_set(X86_FEATURE_DTES64); >> } >> + if (!cpu_has_vmx_arch_lbr()) { >> + kvm_cpu_cap_clear(X86_FEATURE_ARCH_LBR); > No, this needs to be opt-in, not opt-out. I.e. omit the flag from common CPUID > code and set it if and only if it's fully supported. It's not out of the realm > of possibilities that AMD might want to support arch LBRs, at which point those > CPUs would explode. Will modify this patch. > >> + kvm_caps.supported_xss &= ~XFEATURE_MASK_LBR; >> + } >> >> if (!enable_pmu) >> kvm_cpu_cap_clear(X86_FEATURE_PDCM); >> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c >> index 889be0c9176d..38df08d9d0cb 100644 >> --- a/arch/x86/kvm/x86.c >> +++ b/arch/x86/kvm/x86.c >> @@ -217,7 +217,7 @@ static struct kvm_user_return_msrs __percpu *user_return_msrs; >> | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ >> | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) >> >> -#define KVM_SUPPORTED_XSS 0 >> +#define KVM_SUPPORTED_XSS XFEATURE_MASK_LBR >> >> u64 __read_mostly host_efer; >> EXPORT_SYMBOL_GPL(host_efer); >> -- >> 2.27.0 >>
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 359da38a19a1..3bc892e8cf7a 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7733,6 +7733,10 @@ static __init void vmx_set_cpu_caps(void) kvm_cpu_cap_check_and_set(X86_FEATURE_DS); kvm_cpu_cap_check_and_set(X86_FEATURE_DTES64); } + if (!cpu_has_vmx_arch_lbr()) { + kvm_cpu_cap_clear(X86_FEATURE_ARCH_LBR); + kvm_caps.supported_xss &= ~XFEATURE_MASK_LBR; + } if (!enable_pmu) kvm_cpu_cap_clear(X86_FEATURE_PDCM); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 889be0c9176d..38df08d9d0cb 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -217,7 +217,7 @@ static struct kvm_user_return_msrs __percpu *user_return_msrs; | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) -#define KVM_SUPPORTED_XSS 0 +#define KVM_SUPPORTED_XSS XFEATURE_MASK_LBR u64 __read_mostly host_efer; EXPORT_SYMBOL_GPL(host_efer);